Haojian Zhuang 483dce7eef hikey: update ddr initialization ...

Fix that DDR can't work at 533MHz. Now step to set DDR frequency
from 150MHz to 800MHz. DDR could work among these frequency, 150MHz,
266MHz, 400MHz, 533MHz and 800MHz.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

2018-04-11 19:05:32 +08:00

..

arm

Juno: Increase bl2 max size to fix build when SPD=opteed

2018-04-09 17:34:11 +05:30

common

plat: fix switch statements to comply with MISRA rules

2018-03-26 12:43:05 +01:00

compat

Do not enable SVE on pre-v8.2 platforms

2017-11-30 17:45:23 +00:00

hisilicon

hikey: update ddr initialization

2018-04-11 19:05:32 +08:00

layerscape

layerscape: Initial TF-A support for LS1043ardb

2018-04-10 01:24:40 +00:00

mediatek

Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

2018-03-29 13:20:05 +01:00

nvidia/tegra

Clean usage of void pointers to access symbols

2018-03-27 13:20:27 +01:00

qemu

Merge pull request #1334 from michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console

2018-04-03 11:59:55 +01:00

rockchip

Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

2018-03-29 13:20:05 +01:00

rpi3

Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

2018-03-29 13:20:05 +01:00

socionext/uniphier

plat: fix switch statements to comply with MISRA rules

2018-03-26 12:43:05 +01:00

xilinx/zynqmp

plat: fix switch statements to comply with MISRA rules

2018-03-26 12:43:05 +01:00