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6cb426e137
Update EC board configuration for P5 boards : - PMIC_THERM_L GPIO used for PMIC shutdown has moved. - add 5V regulator control (used for VBUS only) - the Type-C superspeed muxes control changed - add a temporary pull-up on EN_PP3300 - add new FW_DEBUG_MODE GPIO Try to be compatible with both P4 and P5 by detecting the board variant at runtime. At EC startup, USBC_SS1_USB_MODE_L/USBC_SS2_USB_MODE_L/USBC_SS_EN_L (aka PD3/PD9/PE0 aka MUX_CONF0/1/2) now default to low level rather than high (as the new default value on P5), but they are reset to the correct value when initializing the PD task (high for P4, low for P5+). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38330 TEST=Ran on P4, check board ID on P5 PCB. Change-Id: Ie9010805a91362c2b4d5eddd825d452d6ccc5b28 Reviewed-on: https://chromium-review.googlesource.com/262310 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>