Aaron Durbin 4d4facda91 falco: peppy: slippy: mark LPC_CLKRUN_L as open drain ...

The LPC_CLKRUN_L signal on these boards has an external pull
up to the correct PCH rail. Therefore, configure the pin
controlling LPC_CLKRUN_L as open drain.

BUG=chrome-os-partner:19811
BUG=chrome-os-partner:20331
BRANCH=None
TEST=Built and flashed. Interrogated GPIOODR register for port M:
     > rw 0x4006350c
     read 0x4006350c = 0x00000004

Change-Id: I50dc90d784bd1d1f318b401e5d7d6e06bf0f1e47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59416
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>

2013-06-20 13:54:38 -07:00

..

bds

Move write protect GPIO handling to flash module

2013-05-23 11:08:44 -07:00

daisy

Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOW

2013-06-13 18:13:23 -07:00

falco

falco: peppy: slippy: mark LPC_CLKRUN_L as open drain

2013-06-20 13:54:38 -07:00

host

Enable flash unit test on emulator

2013-06-03 14:34:10 -07:00

link

Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOW

2013-06-13 18:13:23 -07:00

mccroskey

Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOW

2013-06-13 18:13:23 -07:00

peppy

falco: peppy: slippy: mark LPC_CLKRUN_L as open drain

2013-06-20 13:54:38 -07:00

pit

Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOW

2013-06-13 18:13:23 -07:00

slippy

falco: peppy: slippy: mark LPC_CLKRUN_L as open drain

2013-06-20 13:54:38 -07:00

snow

Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOW

2013-06-13 18:13:23 -07:00

spring

spring: new TPS65090 parameters to avoid cap ringing

2013-06-19 17:12:36 -07:00