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1b53f74664
The new FPGA version adds a lot of few features, while temporarily
cutting off some existing capabilities like clocking configuration
(hardwared clocks used instead), pinmux assignment for SPS interface
(hardwared connections used), etc.
This patch removes some now unused code, modifies some configuration
items and adds TODO_FGPA comment blocks highlighting code which needs
to be reviews next time FPGA version changes).
The new register definitions file is derived from hardware
description.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=with these changes in place the B1 board boots to the console
prompt.
Change-Id: I78ec6b2831a44cbfd40ee726a5d3c2cc11bf2cfa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291855
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
122 lines
2.4 KiB
C
122 lines
2.4 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "pmu.h"
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#include "task.h"
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/*
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* TODO_FPGA this file should be thoroughly reworked when actual support is
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* introduced.
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*/
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/*
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* RC Trim constants
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*/
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#define RCTRIM_RESOLUTION (12)
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#define RCTRIM_LOAD_VAL (1 << 11)
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#define RCTRIM_RANGE_MAX (7 * 7)
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#define RCTRIM_RANGE_MIN (-8 * 7)
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#define RCTRIM_RANGE (RCTRIM_RANGE_MAX - RCTRIM_RANGE_MIN + 1)
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/*
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* Enable peripheral clock
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* @param perih Peripheral from @ref uint32_t
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*/
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void pmu_clock_en(uint32_t periph)
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{
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if (periph <= 31)
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GR_PMU_PERICLKSET0 = (1 << periph);
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else
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GR_PMU_PERICLKSET1 = (1 << (periph - 32));
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}
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/*
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* Disable peripheral clock
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* @param perih Peripheral from @ref uint32_t
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*/
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void pmu_clock_dis(uint32_t periph)
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{
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if (periph <= 31)
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GR_PMU_PERICLKCLR0 = (1 << periph);
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else
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GR_PMU_PERICLKCLR1 = (1 << (periph - 32));
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}
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/*
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* Peripheral reset
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* @param periph Peripheral from @ref uint32_t
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*/
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void pmu_peripheral_rst(uint32_t periph)
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{
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/* Reset high */
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if (periph <= 31)
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GR_PMU_RST0 = 1 << periph;
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else
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GR_PMU_RST1 = 1 << (periph - 32);
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}
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/*
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* enable clock doubler for USB purposes
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*/
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void pmu_enable_clock_doubler(void)
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{
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}
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/*
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* Switch system clock to XO
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* @returns The value of XO_OSC_XTL_FSM_STATUS. 0 = okay, 1 = error.
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*/
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uint32_t pmu_clock_switch_xo(void)
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{
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return 0;
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}
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/*
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* Enter sleep mode and handle exiting from sleep mode
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* @warning The CPU must be in RC no trim mode before calling this function
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*/
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void pmu_sleep(void)
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{
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}
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/*
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* Exit hibernate mode
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* This function should be called after a powerdown exit event.
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* It handles turning the power domains back on.
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* Clocks will be left in RC no trim.
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*/
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void pmu_hibernate_exit(void)
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{
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}
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/*
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* Enter powerdown mode
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* This function does not return. The powerdown exit event will
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* cause the CPU to begin executing the system / app bootloader.
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* @warning The CPU must be in RC no trim mode
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*/
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void pmu_powerdown(void)
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{
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}
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/*
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* Exit powerdown mode
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* This function should be called after a powerdown exit event.
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* It handles turning the power domains back on.
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* Clocks will be left in RC no trim.
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*/
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void pmu_powerdown_exit(void)
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{
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}
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/**
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* Handle PMU interrupt
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*/
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void pmu_interrupt(void)
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{
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/* TBD */
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}
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/* DECLARE_IRQ(GC_IRQNUM_PMU_PMUINT, pmu_interrupt, 1); */
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