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957638c78c
Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
73 lines
2.9 KiB
C
73 lines
2.9 KiB
C
/*
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* Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/*
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* Booter header for Chrome EC.
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*
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* This header is used by Nuvoton EC Booter.
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*/
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#include <stdint.h>
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#include "registers.h"
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#include "config_chip.h"
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/* Signature used by fw header */
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#define SIG_FW_EC 0x2A3B4D5E
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/* Definition used by error detection configuration */
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#define CHECK_CRC 0x00
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#define CHECK_CHECKSUM 0x01
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#define ERROR_DETECTION_EN 0x02
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#define ERROR_DETECTION_DIS 0x00
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/* Code RAM addresses use by header */
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#define FW_START_ADDR CONFIG_CDRAM_BASE /* Put FW at the begin of CODE RAM */
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/* TODO: It will be filled automatically by ECST */
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/* The entry point of reset handler (filled by ECST tool)*/
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#define FW_ENTRY_ADDR 0x100A8169
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/* Error detection addresses use by header (A offset relative to flash image) */
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#define ERRCHK_START_ADDR 0x0
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#define ERRCHK_END_ADDR 0x0
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/* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
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#define FW_SIZE CONFIG_RO_SIZE
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/* FW Header used by NPCX5M5G Booter */
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struct __packed fw_header_t {
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uint32_t anchor; /* A constant used to verify FW header */
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uint16_t ext_anchor; /* Enable/disable firmware header CRC check */
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uint8_t spi_max_freq; /* Spi maximum allowable clock frequency */
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uint8_t spi_read_mode; /* Spi read mode used for firmware loading */
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uint8_t cfg_err_detect; /* FW load error detection configuration */
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uint32_t fw_load_addr; /* Firmware load start address */
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uint32_t fw_entry; /* Firmware entry point */
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uint32_t err_detect_start_addr; /* FW error detect start address */
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uint32_t err_detect_end_addr; /* FW error detect end address */
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uint32_t fw_length; /* Firmware length in bytes */
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uint8_t flash_size; /* Indicate SPI flash size */
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uint8_t reserved[26]; /* Reserved bytes */
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uint32_t sig_header; /* The CRC signature of the firmware header */
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uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */
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} __aligned(1);
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__attribute__ ((section(".header")))
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const struct fw_header_t fw_header = {
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/* 00 */ SIG_FW_EC,
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/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h */
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/* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h */
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/* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
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/* 08 */ 0x00, /* Disable CRC check functionality */
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/* 09 */ FW_START_ADDR,
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/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
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/* 11 */ ERRCHK_START_ADDR,
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/* 15 */ ERRCHK_END_ADDR,
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/* 19 */ FW_SIZE,/* Filling by ECST tool */
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/* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh */
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/* 1E-3F Other fields are filled by ECST tool or reserved */
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};
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