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0e53f9d425
Implemented mec1322's heavysleep in idle task to reduce further EC power down on S3. MEC1322 needs sleep-enabled for all blocks to acheive max power down including UART. Real heavysleep will be effective only when console/uart is not active. To enable this commit, board-specific commit is required. For example, check commit, "Enabling heavysleep idle task at S3". Test: 1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux shell. 2. wait at least 1 min till EC console sleeps 3. measure EC power. Since idle task is continuously scheduled, EC will enters/exits to/from heavy sleep mode frequently in S3 and power consumption will be changed dynamically. For acurate power measurement, high-sampling-rate measurement system might be required and using DMM might not give accurate number. BUG=None TEST=Tested on evt1p0/evt1p7/DVT BRANCH=None Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283603 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and defintions for Cortex-MLM4x processor
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*/
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#ifndef __CROS_EC_CPU_H
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#define __CROS_EC_CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010)
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#define ST_ENABLE (1 << 0)
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#define ST_TICKINT (1 << 1)
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#define ST_CLKSOURCE (1 << 2)
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#define ST_COUNTFLAG (1 << 16)
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
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#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
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#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
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#define CPU_NVIC_CCR CPUREG(0xe000ed14)
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#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
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#define CPU_NVIC_MMFS CPUREG(0xe000ed28)
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#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
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#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
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#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
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#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
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enum {
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CPU_NVIC_MMFS_BFARVALID = 1 << 15,
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CPU_NVIC_MMFS_MFARVALID = 1 << 7,
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CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4,
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CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3,
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CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
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CPU_NVIC_HFSR_FORCED = 1 << 30,
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CPU_NVIC_HFSR_VECTTBL = 1 << 1,
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CPU_NVIC_SHCSR_MEMFAULTENA = 1 << 16,
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CPU_NVIC_SHCSR_BUSFAULTENA = 1 << 17,
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CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18,
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};
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/* Set up the cpu to detect faults */
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void cpu_init(void);
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#endif /* __CROS_EC_CPU_H */
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