Kyösti Mälkki 521d8c2573 Activate older Xeon P4 microcodes ...

As new microcode files were included, the table was not updated with
families 0f25 and 0f26.

Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2011-10-18 00:10:51 +02:00

..

arch/x86

cbfs_and_run_core() is not part of the API, make it static.

2011-10-15 12:27:52 +02:00

boot

use byteorder.h instead of implementing another byte swap function

2011-10-15 16:21:06 +02:00

console

Add support for the tracing infastructure in coreboot.

2011-09-07 01:26:47 +02:00

cpu

Activate older Xeon P4 microcodes

2011-10-18 00:10:51 +02:00

devices

Fix compilation of x86emu with gcc 4.6.x

2011-10-13 20:01:47 +02:00

drivers

Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an

2011-04-26 23:47:04 +00:00

ec

Lenovo H8: Always clear audio mute

2011-08-19 14:17:06 +02:00

include

Enable/fix compilation of i8254 code in ram stage.

2011-10-13 20:00:22 +02:00

lib

refactor vesa mode setting code and bootsplash code

2011-10-13 20:00:50 +02:00

mainboard

Re-worked devicetree.cb for DL145 G1

2011-10-17 09:44:56 +02:00

northbridge

AMD CPU and chipset fixes for compilation with gcc 4.6

2011-10-15 13:40:17 +02:00

pc80

Fix our CMOS checksum algorithm so it matches what /dev/nvram expects

2011-10-17 17:51:52 +02:00

southbridge

AMD CPU and chipset fixes for compilation with gcc 4.6

2011-10-15 13:40:17 +02:00

superio

w83627hf: ASL include containing virtual device tree of the SuperIO

2011-10-12 07:56:29 +02:00

vendorcode

Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6

2011-10-14 22:57:11 +02:00

Kconfig

refactor vesa mode setting code and bootsplash code

2011-10-13 20:00:50 +02:00

Kconfig.deprecated_options

some ifdef --> if fixes

2011-04-21 20:24:43 +00:00