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3ec36e0160
This change configures MPU to prevent instruction fetch from the flash image that is not running at the time system_disable_jump is called. Violating the protection causes instruction access violation, then the EC reboots. RO image protection is tested as follows: ... [6.255696 MPU type: 00000800] [6.255874 RAM locked. Exclusion 20005680-200056a0] [6.256168 RO image locked] ... > sysjump 0 Jumping to 0x00000000 === PROCESS EXCEPTION: 03 ====== xPSR: 60000000 === r0 :00000000 r1 :2000541c r2 :00001388 r3 :20007fe8 r4 :200032f0 r5 :00000000 r6 :20002b70 r7 :20002df4 r8 :0002d308 r9 :20002df4 r10:00000000 r11:00000000 r12:00000002 sp :20002358 lr :0002a1a7 pc :00000000 Instruction access violation, Forced hard fault mmfs = 1, shcsr = 70000, hfsr = 40000000, dfsr = 0 =========== Process Stack Contents =========== 200023c0: 00000098 00000000 00000000 0002a785 200023d0: 00000002 20002dfd 00000007 20002b70 200023e0: 00000002 00025777 00000000 20002dfd 200023f0: 20002df4 20002dfc 00000000 00000000 Rebooting... Memory management fault status register has bit0 set, indicating there was an instruction fetch volation. FYI, RAM protection is still working: > sysjump 0x20000000 Jumping to 0x20000000 === PROCESS EXCEPTION: 03 ====== xPSR: 60000000 === r0 :00000000 r1 :2000541c r2 :00001388 r3 :20007fe8 r4 :200032f0 r5 :20000000 r6 :20002b70 r7 :20002df4 r8 :0002d308 r9 :20002df4 r10:00000000 r11:00000000 r12:00000002 sp :20002358 lr :0002a1a7 pc :20000000 Instruction access violation, Forced hard fault mmfs = 1, shcsr = 70000, hfsr = 40000000, dfsr = 0 =========== Process Stack Contents =========== 200023c0: 00000098 00000000 20000000 0002a785 200023d0: 00000002 20002e06 00000007 20002b70 200023e0: 00000002 00025777 00000000 20002e06 200023f0: 20002df4 20002dfc 00000000 00000000 Rebooting... TEST=Booted Peppy. Tested lid close & open. Ran Flashrom from userspace to update main firmware then software-synched an EC image. BUG=chrome-os-partner:16904 BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Id4f84d24325566a9f648194166bde0d94d1124dc Reviewed-on: https://chromium-review.googlesource.com/169050 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Tested-by: Daisuke Nojiri <dnojiri@google.com>
79 lines
2.0 KiB
C
79 lines
2.0 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MPU module for Cortex-M3 */
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#ifndef __CROS_EC_MPU_H
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#define __CROS_EC_MPU_H
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#include "common.h"
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#define MPU_TYPE REG32(0xe000ed90)
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#define MPU_CTRL REG32(0xe000ed94)
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#define MPU_NUMBER REG32(0xe000ed98)
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#define MPU_BASE REG32(0xe000ed9c)
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#define MPU_SIZE REG16(0xe000eda0)
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#define MPU_ATTR REG16(0xe000eda2)
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#define MPU_CTRL_PRIVDEFEN (1 << 2)
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#define MPU_CTRL_HFNMIENA (1 << 1)
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#define MPU_CTRL_ENABLE (1 << 0)
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/*
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* XN (execute never) bit. It's bit 12 if accessed by halfword.
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* 0: XN off
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* 1: XN on
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*/
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#define MPU_ATTR_XN (1 << 12)
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/* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
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#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */
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#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */
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#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */
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/* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
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* datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
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#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */
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#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */
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/**
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* Enable MPU
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*/
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void mpu_enable(void);
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/**
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* Returns the value of MPU type register
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*
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* Bit fields:
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* [15:8] Number of the data regions implemented or 0 if MPU is not present.
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* [1] 0: unified (no distinction between instruction and data)
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* 1: separated
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*/
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uint32_t mpu_get_type(void);
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/* Location of iram.text */
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extern char __iram_text_start;
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extern char __iram_text_end;
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/**
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* Protect RAM from code execution
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*/
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int mpu_protect_ram(void);
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/**
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* Protect flash memory from code execution
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*/
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int mpu_lock_ro_flash(void);
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int mpu_lock_rw_flash(void);
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/**
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* Initialize MPU.
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* It disables all regions if MPU is implemented. Otherwise, returns
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* EC_ERROR_UNIMPLEMENTED.
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*/
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int mpu_pre_init(void);
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#endif /* __CROS_EC_MPU_H */
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