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d58e54730c
Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
78 lines
2.8 KiB
C
78 lines
2.8 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H
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#define __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H
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/*
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* Standard memory-mapped flash layout:
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* - RO image starts at the beginning of flash.
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* - PSTATE immediately follows the RO image.
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* - RW image starts at the second half of flash.
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* - Protected region consists of the first half of flash (RO image + PSTATE).
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* - Unprotected region consists of second half of flash (RW image).
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*
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* PSTATE
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* |
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* v
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* |<-----Protected Region------>|<------Unprotected Region----->|
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* |<--------RO image--------->| |<----------RW image----------->|
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* 0 N/2 N
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*
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* This layout is used by several supported chips. Chips which do not use
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* this layout MUST NOT include this header file, and must instead define
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* the configs below in a chip-level header file (config_flash_layout.h).
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*
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* See the following page for additional image geometry discussion:
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*
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* https://www.chromium.org/chromium-os/ec-development/ec-image-geometry-spec
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*
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* TODO(crosbug.com/p/23796): Finish implementing the spec.
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*/
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/* Memory-mapped internal flash w/ PSTATE */
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#define CONFIG_INTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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#define CONFIG_FLASH_PSTATE
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/* Program is run directly from storage */
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#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
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/*
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* The EC uses the one bank of flash to emulate a SPI-like write protect
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* register with persistent state.
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*/
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#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
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#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
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/* Size of one firmware image in flash */
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#define CONFIG_FW_IMAGE_SIZE ((CONFIG_FLASH_PHYSICAL_SIZE - \
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CONFIG_SHAREDLIB_SIZE) / 2)
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#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
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/*
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* By default, there is no shared objects library. However, if configured, the
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* shared objects library will be placed after the RO image.
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*/
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#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + \
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CONFIG_FW_IMAGE_SIZE)
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#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + \
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CONFIG_FW_IMAGE_SIZE)
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#define CONFIG_SHAREDLIB_SIZE 0
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_STORAGE_OFF 0
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#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
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#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + \
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CONFIG_SHAREDLIB_SIZE)
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#define CONFIG_RW_STORAGE_OFF (CONFIG_SHAREDLIB_STORAGE_OFF + \
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CONFIG_SHAREDLIB_SIZE)
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#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
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#define CONFIG_WP_OFF CONFIG_RO_STORAGE_OFF
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#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
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#endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */
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