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57ad82c274
In current FW implement, there are two ways to generate SMI/SCI:
(1) Controlled by GPIO module register.(#define CONFIG_SCI_GPIO)
(2) Controlled by PM module register.(#undef CONFIG_SCI_GPIO)
This CL fix for case(2):
In this case, these two dedicated pins(GPIOC6/GPIO76) are used
as SMI/SCI and must be enabled by pinmux. Set the related pinmux
at initial.
By default, the SMI/SCI polarity is negative. This means SMI/SCI
is inverted when writing to SMI/SCIB but not inverted when reading
from them(see Section 5.2.2, figure 61 in datasheet). It will cause
the code more complicated to implement. Disable negative polarity
at init.
Modified drivers:
1. lpc.c: set pinmux for dedicated SMI/SCI pins and disable the
negative polarity.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent(lid switch) on Wheatley with
CONFIG_SCL_GPIO undefined.
Change-Id: Ia317e54deb6861d7189b3594bd7414b53408b933
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396718
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>