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629c3964a2
We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
79 lines
2.4 KiB
ArmAsm
79 lines
2.4 KiB
ArmAsm
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "config.h"
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#include "rwsig.h"
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OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
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OUTPUT_ARCH(BFD_ARCH)
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MEMORY
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{
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FLASH (rx) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE, LENGTH = CONFIG_FLASH_SIZE
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}
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SECTIONS
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{
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. = ALIGN(CONFIG_FLASH_BANK_SIZE);
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#if defined(NPCX_RO_HEADER)
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/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header
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* or some struture which doesn't belong to FW */
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.image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF\
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) {
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#else
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.image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF) {
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#endif
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*(.image.RO)
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} > FLASH =0xff
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. = ALIGN(CONFIG_FLASH_BANK_SIZE);
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#ifdef CONFIG_RWSIG_TYPE_RWSIG
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.image.RO.key : AT(CONFIG_RO_PUBKEY_ADDR) {
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*(.image.RO.key)
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} > FLASH =0xff
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#endif
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#ifdef CONFIG_ROLLBACK
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.image.ROLLBACK : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_ROLLBACK_OFF) {
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*(.image.ROLLBACK)
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} > FLASH =0xff
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#endif
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#ifdef CONFIG_SHAREDLIB
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.image.libsharedobjs : AT(CONFIG_PROGRAM_MEMORY_BASE + \
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CONFIG_SHAREDLIB_MEM_OFF) {
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*(.image.libsharedobjs)
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} > FLASH =0xff
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. = ALIGN(CONFIG_FLASH_BANK_SIZE);
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#endif
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#if defined(NPCX_RO_HEADER)
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/* npcx uses *STORAGE_OFF to plan the layout of flash image */
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.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF \
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+ CONFIG_RW_STORAGE_OFF) {
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#elif (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
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/* This is applicable to ECs in which RO and RW execution is
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mapped to the same location but we still have to generate an ec.bin with RO
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and RW images at different Flash offset */
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.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF + \
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CONFIG_RO_SIZE) {
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#else
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.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF) {
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#endif
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*(.image.RW)
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} > FLASH =0xff
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#ifdef CONFIG_RWSIG_TYPE_RWSIG
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.image.RW.sign : AT(CONFIG_RW_SIG_ADDR) {
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*(.image.RW.sign)
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} > FLASH =0xff
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#endif
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#ifdef CONFIG_RW_B_MEM_OFF
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.image.RW_B : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_B_MEM_OFF) {
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*(.image.RW_B)
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} > FLASH =0xff
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#endif
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.padding : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE - 1) {
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BYTE(0xff);
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} > FLASH =0xff
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}
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