Stefan Reinauer 5c55463f50 Add support for Intel Sandybridge CPU ...

Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/855
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2012-04-05 21:10:25 +02:00

..

car

Whitespace fixes

2012-03-31 18:06:09 +02:00

ep80579

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

hyperthreading

Intel cpus: Fix deadlock on hyper-threading init

2012-03-25 20:33:28 +02:00

microcode

Add support for Intel Sandybridge CPU

2012-04-05 21:10:25 +02:00

model_6bx

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_6dx

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_6ex

Intel cpus: Include CAR from socket

2012-03-17 09:38:31 +01:00

model_6fx

Intel cpus: use CPU_PHYSMASK_HI define in CAR

2012-02-16 01:55:50 +01:00

model_6xx

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_65x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_67x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_68x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_69x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_106cx

Intel cpus: use CPU_PHYSMASK_HI define in CAR

2012-02-16 01:55:50 +01:00

model_206ax

Add support for Intel Sandybridge CPU

2012-04-05 21:10:25 +02:00

model_1067x

Intel cpus: apply un-written naming rules

2012-02-10 23:40:07 +01:00

model_f0x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_f1x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_f2x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_f3x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

model_f4x

MTRR: get physical address size from CPUID

2012-01-10 21:51:40 +01:00

slot_1

cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.

2011-08-04 08:10:12 +02:00

slot_2

Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.

2010-10-15 07:47:51 +00:00

socket_441

oops. this is weird. CAR addresses should be specified in the socket and not in

2011-01-27 01:11:20 +00:00

socket_BGA956

Intel cpus: apply un-written naming rules

2012-02-10 23:40:07 +01:00

socket_FC_PGA370

Get rid of the old romstage-as-bootblock ROM layout

2011-10-28 22:17:36 +02:00

socket_LGA771

Intel cpus: Include CAR from socket

2012-03-17 09:38:31 +01:00

socket_mFCBGA479

Move "select CACHE_AS_RAM" lines from boards into CPU socket.

2010-12-08 08:22:04 +00:00

socket_mFCPGA478

Intel cpus: Include CAR from socket

2012-03-17 09:38:31 +01:00

socket_mPGA478

Rename build system variables to be more intuitive, and

2010-09-30 16:55:02 +00:00

socket_mPGA479M

Move "select CACHE_AS_RAM" lines from boards into CPU socket.

2010-12-08 08:22:04 +00:00

socket_mPGA603

Rename build system variables to be more intuitive, and

2010-09-30 16:55:02 +00:00

socket_mPGA604

Apply cache-as-ram conditionally on socket mPGA604

2012-04-02 21:13:26 +02:00

socket_PGA370

Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.

2010-10-15 07:47:51 +00:00

socket_rPGA989

Add support for Intel Sandybridge CPU

2012-04-05 21:10:25 +02:00

speedstep

ACPI: mark empty get_cst_entries() weak

2012-01-09 11:07:18 +01:00

thermal_monitoring

drop unused code (trivial)

2008-08-01 11:53:39 +00:00

turbo

Add support for Intel Turbo Boost feature

2012-04-03 20:29:33 +02:00

Kconfig

Add support for Intel Sandybridge CPU

2012-04-05 21:10:25 +02:00

Makefile.inc

Add support for Intel Sandybridge CPU

2012-04-05 21:10:25 +02:00