Martin Roth 5cf5828c02 fsp1_0: Remove hardcoded microcode locations ...

These are no longer needed.

Test: Booted minnowmax.

Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12468
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

2015-11-20 16:36:08 +01:00

..

acpi

tree: drop last paragraph of GPL copyright header

2015-10-31 21:37:39 +01:00

arch

arm64: tegra132: tegra210: Remove old arm64/stage_entry.S

2015-11-17 21:31:20 +01:00

commonlib

vendorcode/google/chromeos: Cache VPD data into CBMEM

2015-11-19 21:37:47 +01:00

console

x86: Add Kconfig to disable early bootblock postcodes

2015-11-19 00:16:50 +01:00

cpu

fsp1_0: Remove hardcoded microcode locations

2015-11-20 16:36:08 +01:00

device

device/device.c: remove warning for missing apic read resources

2015-11-19 14:46:43 +01:00

drivers

intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit

2015-11-16 17:42:36 +01:00

ec

tree: drop last paragraph of GPL copyright header

2015-10-31 21:37:39 +01:00

include

rules.h: Add ENV_ macros to detect current architecture

2015-11-17 21:31:07 +01:00

lib

vendorcode/google/chromeos: Cache VPD data into CBMEM

2015-11-19 21:37:47 +01:00

mainboard

siemens/mc_tcu3: Clear checksums in hwinfo

2015-11-20 16:13:55 +01:00

northbridge

nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset

2015-11-19 21:43:31 +01:00

soc

fsp1_0: Remove hardcoded microcode locations

2015-11-20 16:36:08 +01:00

southbridge

southbridge/amd: add support for Bolton FCH

2015-11-20 16:35:47 +01:00

superio

Revert "Drop SuperIO nuvoton/nct6779d"

2015-11-16 17:44:54 +01:00

vendorcode

vendorcode/google/chromeos: Cache VPD data into CBMEM

2015-11-19 21:37:47 +01:00

Kconfig

Remove dependency for HAS_PRECBMEM_TIMESTAMP_REGION

2015-11-18 23:22:11 +01:00