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5d208b9924
The STM32F0 has a fancier SPI than the L1 series we've been using so far. Notably it supports 16 bit data packing. This mode is activated automatically by reading/writing to the SPI_DR register as 16 bits. We do not want this feature since we only do 8 bit operations. This change prevents a misalignment of the data where the MCU thinks it's doing 16 bit transfers and we want 8 bit transfers. Another unwanted feature is the FIFO. We rely on DMA and some buffers instead. Keeping the FIFO enabled causes extra characters. The way this patch disables the fifo is by changing the FIFO reception threshold to only 1 byte (which is the same behavior that L1 has with no FIFO). Setting the FRXTH bit on the L1 chips should not affect anything as that area of the register is reserved. BUG=none BRANCH=none TEST=Try SPI on both STM32L1xx(preexisting support, should not be broken) and STM32F0(new support/veyron) Change-Id: I90dc6bb8a82881e70058443591acaebc44ba982b Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/211476 Reviewed-by: Doug Anderson <dianders@chromium.org>