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b39f6780a1
We disable i2c interface immediately after stop bit is set. This might caused bus busy bit of status register unable to clear (bus busy bit will be set at start condition and cleared at stop condition). So the next transaction, we won't get a good state to start. This change also fix incorrect stop bit for write transaction: IT83XX_I2C_CTR(p_ch) = xx BRANCH=none BUG=none TEST=Ensure i2c interface is disabled after i2c stop condition. Change-Id: I5416bfcef3f95357c6771dead6b0611b908f787e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/645407 Reviewed-by: Randall Spangler <rspangler@chromium.org>