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https://github.com/Telecominfraproject/OpenCellular.git
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14bd917343
Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* CPU core BFD configuration */
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#include "core/cortex-m/config_core.h"
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/* 32k hz internal oscillator frequency (FRCLK) */
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#define INT_32K_CLOCK 32768
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 64
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/* Use a bigger console output buffer */
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 8192
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/*
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* Interval between HOOK_TICK notifications
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* Notice instant wake-up from deep-idle cannot exceed 200 ms
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*/
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#define HOOK_TICK_INTERVAL_MS 200
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* Maximum number of deferrable functions */
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#define DEFERRABLE_MAX_COUNT 8
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/* Number of I2C ports */
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#define I2C_PORT_COUNT 4
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/* Number of PWM ports */
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#define PWM_COUNT 8
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/*****************************************************************************/
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/* Memory mapping */
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#define CONFIG_RAM_BASE 0x200C0000 /* memory map address of data ram */
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#define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */
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#define CONFIG_CDRAM_BASE 0x100A8000 /* memory map address of code ram */
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#define CONFIG_CDRAM_SIZE 0x00018000 /* 96KB code ram */
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#define CONFIG_FLASH_BASE 0x64000000 /* memory address of spi-flash */
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#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of low power ram */
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#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */
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/* System stack size */
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#define CONFIG_STACK_SIZE 4096
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/* non-standard task stack sizes */
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#define IDLE_TASK_STACK_SIZE 512
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#define LARGER_TASK_STACK_SIZE 640
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#define CHARGER_TASK_STACK_SIZE 640
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#define HOOKS_TASK_STACK_SIZE 640
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#define CONSOLE_TASK_STACK_SIZE 640
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/* Default task stack size */
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#define TASK_STACK_SIZE 512
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/* Address of RAM log used by Booter */
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#define ADDR_BOOT_RAMLOG 0x100C7FC0
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/* SPI Flash Spec of W25Q20CV */
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#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size 4K bytes */
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#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* sector erase size 4K bytes */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000001 /* minimum write size */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
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/* 128 KB alignment for SPI status registers protection */
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#define CONFIG_FLASH_PHYSICAL_SIZE 0x40000 /* 256 KB Flash used for EC */
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/* No PSTATE; uses a real SPI flash */
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#undef CONFIG_FLASH_PSTATE
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/* Header support which is used by booter to copy FW from flash to code ram */
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#define NPCX_RO_HEADER
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/****************************************************************************/
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/* Define npcx flash layout. */
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/* Size of one firmware image in flash */
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#ifndef CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2)
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#endif
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/* The storage offset of ec.RO.flat which is used for CONFIG_CDRAM_ARCH */
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#define CONFIG_RO_STORAGE_OFF 0
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#ifdef NPCX_RO_HEADER
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#define CONFIG_RO_HDR_MEM_OFF 0x0
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#define CONFIG_RO_HDR_SIZE 0x40
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/* RO firmware offset in flash */
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#define CONFIG_RO_MEM_OFF CONFIG_RO_HDR_SIZE
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#else
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#define CONFIG_RO_MEM_OFF 0x0
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#endif
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#define CONFIG_RO_SIZE CONFIG_CDRAM_SIZE /* 96KB for RO FW */
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#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
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/* The storage offset of ec.RW.flat which is used for CONFIG_CDRAM_ARCH */
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#define CONFIG_RW_STORAGE_OFF CONFIG_FW_IMAGE_SIZE /* 128 KB alignemnt */
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/* RW firmware offset in flash */
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#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF
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#define CONFIG_RW_SIZE CONFIG_CDRAM_SIZE /* 96KB for RW FW */
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#define CONFIG_WP_OFF CONFIG_RO_STORAGE_OFF
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#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
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/****************************************************************************/
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/* Customize the build */
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/* Optional features present on this chip */
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#define CONFIG_ADC
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#define CONFIG_FPU
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#define CONFIG_I2C
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#define CONFIG_PECI
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#define CONFIG_SWITCH
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#define CONFIG_MPU
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/* Compile for running from RAM instead of flash */
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/* #define COMPILE_FOR_RAM */
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#define GPIO_PIN(port, index) GPIO_##port, (1 << index)
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#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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