Lee Leahy 1d14b3e926 soc/intel: Add Skylake SOC support ...

Add the files to support the Skylake SOC.
Matches chromium tree at 927026db

BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform

Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2015-07-16 17:24:48 +02:00

..

acpi

acpi/sata: add generic sata ssdt port generator

2015-06-07 01:24:47 +02:00

arch

cbfs: hardcode file alignment

2015-07-15 16:34:37 +02:00

console

consoles: remove unused infrastructure

2015-05-26 19:02:54 +02:00

cpu

amd/model_fxx rev.F: emit P-states when no intermediates exist

2015-07-15 19:03:43 +02:00

device

x86 realmode: Set up the 8254 timer before running option rom

2015-07-16 04:03:45 +02:00

drivers

Verify Kconfigs symbols are not zero for hex and int type symbols

2015-07-12 19:06:44 +02:00

ec

ec/lenovo/h8: silence sound on boot

2015-07-07 02:40:50 +02:00

include

cbfs: hardcode file alignment

2015-07-15 16:34:37 +02:00

lib

cbfs: hardcode file alignment

2015-07-15 16:34:37 +02:00

mainboard

AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST check

2015-07-16 04:02:54 +02:00

northbridge

intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152

2015-07-14 12:22:08 +02:00

soc

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

southbridge

azalia: fix up and clean up shrinkage of boilerplate code

2015-07-14 13:40:07 +02:00

superio

superio/smsc: Add support for SMSC DME1737

2015-07-13 17:11:00 +02:00

vendorcode

cbfs: hardcode file alignment

2015-07-15 16:34:37 +02:00

Kconfig

riscv-emulation: Set stack size to 0 in Kconfig

2015-07-14 16:56:25 +02:00