Nico Huber 654cc2fe10 {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate ...

Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

2018-05-31 15:10:21 +00:00

..

acpi

arch/x86: Add common AMD ACPI hardware definitions

2017-11-10 19:15:38 +00:00

arch

arch/x86: Define HPET_ADDRESS_OVERRIDE

2018-05-28 16:10:28 +00:00

commonlib

Introduce bootblock self-decompression

2018-05-22 02:44:14 +00:00

console

Introduce bootblock self-decompression

2018-05-22 02:44:14 +00:00

cpu

{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

2018-05-31 15:10:21 +00:00

device

device: Move find_dev_path() to device_const.c

2018-05-25 02:45:17 +00:00

drivers

{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

2018-05-31 15:10:21 +00:00

ec

chromeec platforms: Update ACPI throttle handler call

2018-05-29 22:35:07 +00:00

include

cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB

2018-05-31 15:09:30 +00:00

lib

Remove AMD K8 cpu and northbridge support

2018-05-31 03:42:11 +00:00

mainboard

cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE

2018-05-31 15:08:48 +00:00

northbridge

{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

2018-05-31 15:10:21 +00:00

security

security/vboot: Remove redundent _verstage/_everstage/_verstage_size symbols

2018-05-14 16:24:28 +00:00

soc

{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

2018-05-31 15:10:21 +00:00

southbridge

Remove VIA vt8237r southbridge support

2018-05-31 03:47:24 +00:00

superio

superio/ite/it8720f: Implement power control

2018-05-15 11:47:14 +00:00

vendorcode

Remove leftover AMD CIMX RD890 vendorcode

2018-05-24 13:21:32 +00:00

Kconfig

cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE

2018-05-31 15:08:48 +00:00