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65b05ac7b1
Gemini Lake-based chipsets support a subset of virtual wires that other Intel processors do. The current settings prevent the GLK APs from bootign in some situations; PLTRST# doesn't get reasserted when there is an error. See "eSPI Compatibility Specification (562633)" for details. BRANCH=None BUG=b:79778835 TEST=Successfully booted bip after a cold reset from servo Change-Id: I02b403ab6b06cbcae61ac46132018e95988a3d43 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1064704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>