Files
OpenCellular/common/main.c
Mary Ruthven 6672aa1be1 cr50: enable case closed debug
This change adds a ccd console command to control the usb endpoints.
The uart console command is moved into this command so 'ccd uart
[enable|disable]' controls the AP and EC TX signals instead of the
'uart' console command. CCD can be enabled using 'ccd enable'. This
switches the PHY used by the USB controller to be the external PHY.
Changing the PHY exposes the cr50, AP, and EC consoles as well as the
upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles
will be read only until 'ccd uart enable' is called. Cr50 can be updated
using the usb upgrade endpoint. The EC and AP can be updated using the
USB SPI endpoint.

When CCD is disabled the usb controller will switch to using the AP PHY.
None of the endpoints will be visible to the host.

The USB SPI endpoint can be used to flash the EC or AP using
'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled
running flashrom using the raiden_debug_spi programmer will fail. Cr50
will not forward the commands to the external AP or EC ROM, so flashrom
will not be able to find the chip.

The UART TX signals are now controlled by the 'ccd uart' console
command instead of the 'uart' console command. The UART TX is enabled
separately from CCD, because we want to be able to enable CCD while
servo is connected, and having the cr50 UART TX pins wired directly to
the Servo TX lines could damage both devices. The AP and EC consoles
are be read only until 'ccd uart enable' is called. 'ccd uart disable'
disconnects the AP and EC TX pins from the UART peripheral.

When RDD becomes reliable on cr50, ccd_set_mode will select the PHY
being used by the g chip USB controller.

BUG=chrome-os-partner:49960,chrome-os-partner:52281
BRANCH=none
TEST=manual
	TEST SERVO
	power cycle the DUT

	connect servo and check that the AP and EC consoles still work
	check that both the AP and EC can be flashed using servo.

	TEST SUZY Q
	Attach Suzy Q

	Connect to the all three consoles. Check that the cr50 console
	is in read-write mode and the EC and AP consoles are read only.

	Attach Servo.

	Verify all of the servo functionality described above still
	works with suzy q attached and ccd enabled.

	Disconnect Servo.

	run 'ccd uart enable' on the cr50 console and check both the AP
	and EC consoles can be written to.

	Check that the AP and EC can be programmed using the
	raiden_debug_spi programmer.

Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342563
2016-06-03 20:14:59 -07:00

179 lines
4.8 KiB
C

/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Main routine for Chrome EC
*/
#include "board_config.h"
#include "clock.h"
#include "common.h"
#include "console.h"
#include "cpu.h"
#include "dma.h"
#include "eeprom.h"
#include "flash.h"
#include "gpio.h"
#include "hooks.h"
#include "jtag.h"
#include "keyboard_scan.h"
#ifdef CONFIG_MPU
#include "mpu.h"
#endif
#include "rsa.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
#include "watchdog.h"
/* Console output macros */
#define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
test_mockable __keep int main(void)
{
#ifdef CONFIG_REPLACE_LOADER_WITH_BSS_SLOW
/*
* Now that we have started execution, we no longer need the loader.
* Instead, variables placed in the .bss.slow section will use this
* space. Therefore, clear out this region now.
*/
memset((void *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_LOADER_MEM_OFF), 0,
CONFIG_LOADER_SIZE);
#endif /* defined(CONFIG_REPLACE_LOADER_WITH_BSS_SLOW) */
/*
* Pre-initialization (pre-verified boot) stage. Initialization at
* this level should do as little as possible, because verified boot
* may need to jump to another image, which will repeat this
* initialization. In particular, modules should NOT enable
* interrupts.
*/
#ifdef CONFIG_BOARD_PRE_INIT
board_config_pre_init();
#endif
#ifdef CONFIG_MPU
mpu_pre_init();
#endif
/* Configure the pin multiplexers and GPIOs */
jtag_pre_init();
gpio_pre_init();
#ifdef CONFIG_BOARD_POST_GPIO_INIT
board_config_post_gpio_init();
#endif
/*
* Initialize interrupts, but don't enable any of them. Note that
* task scheduling is not enabled until task_start() below.
*/
task_pre_init();
/*
* Initialize the system module. This enables the hibernate clock
* source we need to calibrate the internal oscillator.
*/
system_pre_init();
system_common_pre_init();
#ifdef CONFIG_FLASH
/*
* Initialize flash and apply write protect if necessary. Requires
* the reset flags calculated by system initialization.
*/
flash_pre_init();
#endif
#if defined(CONFIG_CASE_CLOSED_DEBUG) && defined(CONFIG_USB_POWER_DELIVERY)
/*
* If the device is locked we assert PD_NO_DEBUG, preventing the EC
* from interfering with the AP's access to the SPI flash.
* The PD_NO_DEBUG signal is latched in hardware, so changing this
* GPIO later has no effect.
*/
gpio_set_level(GPIO_PD_DISABLE_DEBUG, system_is_locked());
#endif
/* Set the CPU clocks / PLLs. System is now running at full speed. */
clock_init();
/*
* Initialize timer. Everything after this can be benchmarked.
* get_time() and udelay() may now be used. usleep() requires task
* scheduling, so cannot be used yet. Note that interrupts declared
* via DECLARE_IRQ() call timer routines when profiling is enabled, so
* timer init() must be before uart_init().
*/
timer_init();
/* Main initialization stage. Modules may enable interrupts here. */
cpu_init();
#ifdef CONFIG_DMA
/* Initialize DMA. Must be before UART. */
dma_init();
#endif
/* Initialize UART. Console output functions may now be used. */
uart_init();
if (system_jumped_to_this_image()) {
CPRINTS("UART initialized after sysjump");
} else {
CPUTS("\n\n--- UART initialized after reboot ---\n");
CPUTS("[Reset cause: ");
system_print_reset_flags();
CPUTS("]\n");
}
CPRINTF("[Image: %s, %s]\n",
system_get_image_copy_string(), system_get_build_info());
#ifdef CONFIG_BRINGUP
ccprintf("\n\nWARNING: BRINGUP BUILD\n\n\n");
#endif
#ifdef CONFIG_WATCHDOG
/*
* Intialize watchdog timer. All lengthy operations between now and
* task_start() must periodically call watchdog_reload() to avoid
* triggering a watchdog reboot. (This pretty much applies only to
* verified boot, because all *other* lengthy operations should be done
* by tasks.)
*/
watchdog_init();
#endif
/*
* Verified boot needs to read the initial keyboard state and EEPROM
* contents. EEPROM must be up first, so keyboard_scan can toggle
* debugging settings via keys held at boot.
*/
#ifdef CONFIG_EEPROM
eeprom_init();
#endif
#ifdef HAS_TASK_KEYSCAN
keyboard_scan_init();
#endif
#ifdef CONFIG_RWSIG
/*
* Check the RW firmware signature
* and eventually jump to it if it is good.
*/
check_rw_signature();
#endif
/*
* Print the init time. Not completely accurate because it can't take
* into account the time before timer_init(), but it'll at least catch
* the majority of the time.
*/
CPRINTS("Inits done");
/* Launch task scheduling (never returns) */
return task_start();
}