OpenCellular

mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2025-12-27 18:25:05 +00:00

Files

Subrata Banik 68d5d8b28a soc/intel/skylake: Do cache as ram and prepare for C entry

Enable cache-as-ram and prepare for c entry in bootblock.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A

Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>

Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-07-28 05:14:38 +02:00

acpi

arch/x86: provide common Intel ACPI hardware definitions

2016-07-15 08:31:21 +02:00

arch

arch/x86: Add bootblock and postcar support for SOC MTRR access

2016-07-27 13:50:39 +02:00

commonlib

cbmem: share additional time stamps IDs

2016-07-20 22:09:24 +02:00

console

console/post: be explicit about conditional cmos_post_log() compiling