Edward O'Callaghan 728ff392e7 cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs ...

Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

2014-08-09 18:04:32 +02:00

..

allwinner

src: Make use of 'CEIL_DIV(a, b)' macro across tree

2014-07-11 08:39:07 +02:00

amd

cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs

2014-08-09 18:04:32 +02:00

armltd

Introduce stage-specific architecture for coreboot

2014-05-06 20:23:31 +02:00

dmp

Introduce stage-specific architecture for coreboot

2014-05-06 20:23:31 +02:00

intel

cpu/intel: Fix out-of-bounds read due to off-by-one in condition

2014-08-04 13:58:14 +02:00

qemu-x86

Introduce stage-specific architecture for coreboot

2014-05-06 20:23:31 +02:00

samsung

Exynos5420: clean up SPI driver

2014-08-09 17:36:40 +02:00

ti

Introduce stage-specific architecture for coreboot

2014-05-06 20:23:31 +02:00

via

Drop redundant select CACHE_AS_RAM

2014-07-05 11:33:23 +02:00

x86

cpu/x86/lapic/lapic.c: trivial: fix comment on #else

2014-08-03 09:57:50 +02:00

Kconfig

Move ARCH_* from board/Kconfig to cpu or soc Kconfig.

2014-05-03 00:25:20 +02:00

Makefile.inc

Introduce stage-specific architecture for coreboot

2014-05-06 20:23:31 +02:00