Shawn Nematbakhsh 72b8d6f199 npcx: shi: Properly mux pins as GPIO when disabling SHI ...

MODULE_SHI is used for the SPI master interface pins, so don't
reconfigure those. Instead manually configure the SHI pins using the
appropriate DEVALT bit.

BUG=chrome-os-partner:54328
BRANCH=None
TEST=Manual on kevin. Verify SHI continues to function on cold boot,
sysjump and resume from S3. Verify SPI sensors now function on resume
from S3 - `accelinit 0` succeeds.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I63f028968f3d0dbc9d7ca7dacc70c9c399f7a180
Reviewed-on: https://chromium-review.googlesource.com/362061
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>

2016-07-21 00:47:54 -07:00

..

g

g: add an option to disable uart0 rx no matter what

2016-07-20 22:22:09 -07:00

host

NvMem: Added NV Memory module to ec/common/

2016-05-26 16:17:27 -07:00

it83xx

it83xx: Fix timer observation register latch issue

2016-07-19 18:34:03 -07:00

lm4

Cleanup: gate RTC console/host command behind new config options

2016-06-29 21:32:00 -07:00

mec1322

servo_v4: Fix ADC console command

2016-05-26 16:17:26 -07:00

npcx

npcx: shi: Properly mux pins as GPIO when disabling SHI

2016-07-21 00:47:54 -07:00

nrf51

nrf51: update I2C to use PPI code.

2016-07-20 22:22:08 -07:00

stm32

stm32: i2c: Busy loop for a while waiting for interrupt

2016-06-02 14:06:52 -07:00