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ebf92ecc83
On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep and EC is eligable to enter heavy sleep idle task. Wakeup from S0ix by lid open, any key press, power button or track pad will be done by PCH block by asserting SLP_S0. At S0ix, 1 msec pulse will be generated every 8sec and this signal should be ignored since this is NOT S0ix entry/exit related and defered interrupt for SLP_S0 were added. BRANCH=master BUG=none TEST=in OS shell, run following commands. Following command is valid with coreboot with S0ix patches. "echo freeze > /sys/power/state" then, Measure EC power consumption and compare it with one in S0. And on EC console, there should be NO periodic message, "power state 4 = S0ix, in 0x001d" every 8 sec. Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307947 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/*
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* Chipset module for Chrome EC.
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*
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* This is intended to be a platform/chipset-neutral interface, implemented by
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* all main chipsets (x86, gaia, etc.).
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*/
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#ifndef __CROS_EC_CHIPSET_H
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#define __CROS_EC_CHIPSET_H
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#include "common.h"
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#include "gpio.h"
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/*
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* Chipset state mask
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*
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* Note that this is a non-exhaustive list of states which the main chipset can
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* be in, and is potentially one-to-many for real, underlying chipset states.
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* That's why chipset_in_state() asks "Is the chipset in something
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* approximating this state?" and not "Tell me what state the chipset is in and
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* I'll compare it myself with the state(s) I want."
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*/
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enum chipset_state_mask {
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CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */
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CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5) */
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CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */
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CHIPSET_STATE_ON = 0x08, /* On (S0) */
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CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */
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/* Common combinations */
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CHIPSET_STATE_ANY_OFF = (CHIPSET_STATE_HARD_OFF |
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CHIPSET_STATE_SOFT_OFF), /* Any off state */
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};
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#ifdef HAS_TASK_CHIPSET
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/**
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* Check if chipset is in a given state.
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*
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* @param state_mask Combination of one or more CHIPSET_STATE_* flags.
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*
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* @return non-zero if the chipset is in one of the states specified in the
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* mask.
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*/
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int chipset_in_state(int state_mask);
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/**
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* Ask the chipset to exit the hard off state.
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*
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* Does nothing if the chipset has already left the state, or was not in the
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* state to begin with.
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*/
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void chipset_exit_hard_off(void);
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/* This is a private chipset-specific implementation for use only by
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* throttle_ap() . Don't call this directly!
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*/
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void chipset_throttle_cpu(int throttle);
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/**
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* Immediately shut off power to main processor and chipset.
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*
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* This is intended for use when the system is too hot or battery power is
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* critical.
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*/
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void chipset_force_shutdown(void);
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/**
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* Reset the CPU and/or chipset.
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*
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* @param cold_reset If !=0, force a cold reset of the CPU and chipset;
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* if 0, just pulse the reset line to the CPU.
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*/
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void chipset_reset(int cold_reset);
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/**
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* Interrupt handler to power GPIO inputs.
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*/
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void power_interrupt(enum gpio_signal signal);
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#else /* !HAS_TASK_CHIPSET */
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/*
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* Allow other modules to compile if the chipset module is disabled. This is
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* commonly done during early stages of board bringup.
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*/
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static inline int chipset_in_state(int state_mask)
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{
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return 0;
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}
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static inline void chipset_exit_hard_off(void) { }
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static inline void chipset_throttle_cpu(int throttle) { }
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static inline void chipset_force_shutdown(void) { }
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static inline void chipset_reset(int cold_reset) { }
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static inline void power_interrupt(enum gpio_signal signal) { }
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#endif /* !HAS_TASK_CHIPSET */
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#endif /* __CROS_EC_CHIPSET_H */
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