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f23f45e74e
The ARMv7-M ISA defines standard (and optional) mechanism to manage the CPU caches through the SCB (System Control Block) registers. So far, only the Cortex-M7 core implements such as a mechanism (e.g. the Cortex-M4 with caches we have are using a proprietary mechanism for the management). Define the functions to use the I-Cache, and enable them on STM32H7 which is our only supported Cortex-M7 core. The D-Cache mechanism is still To Be Done, as it involves a bit more support in the firmware for the DMA memory areas. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR (e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload without crash and with a speed-up. Change-Id: I6af1021d65048b787630387f7d95797db15d069c Reviewed-on: https://chromium-review.googlesource.com/943445 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and definitions for Cortex-MLM4x processor
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*/
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#ifndef __CROS_EC_CPU_H
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#define __CROS_EC_CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010)
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#define ST_ENABLE (1 << 0)
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#define ST_TICKINT (1 << 1)
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#define ST_CLKSOURCE (1 << 2)
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#define ST_COUNTFLAG (1 << 16)
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
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#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
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#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
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#define CPU_NVIC_CCR CPUREG(0xe000ed14)
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#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
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#define CPU_NVIC_MMFS CPUREG(0xe000ed28)
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#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
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#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
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#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
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#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
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enum {
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CPU_NVIC_MMFS_BFARVALID = 1 << 15,
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CPU_NVIC_MMFS_MFARVALID = 1 << 7,
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CPU_NVIC_CCR_ICACHE = 1 << 17,
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CPU_NVIC_CCR_DCACHE = 1 << 16,
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CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4,
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CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3,
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CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
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CPU_NVIC_HFSR_FORCED = 1 << 30,
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CPU_NVIC_HFSR_VECTTBL = 1 << 1,
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CPU_NVIC_SHCSR_MEMFAULTENA = 1 << 16,
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CPU_NVIC_SHCSR_BUSFAULTENA = 1 << 17,
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CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18,
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};
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/* System Control Block: cache registers */
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#define CPU_SCB_CCSIDR CPUREG(0xe000ed80)
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#define CPU_SCB_CCSELR CPUREG(0xe000ed84)
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#define CPU_SCB_ICIALLU CPUREG(0xe000ef50)
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#define CPU_SCB_DCISW CPUREG(0xe000ef60)
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/* Set up the cpu to detect faults */
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void cpu_init(void);
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/* Enable the CPU instruction cache if it is not already enabled */
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void cpu_enable_icache(void);
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#endif /* __CROS_EC_CPU_H */
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