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If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done() and lpc_sib_wait_host_write_done() routines, in rare case, ec might have a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD bits are high forever. (Normally, CSWR/CSRD bits won't be always high. These bits are high forever also means something wrong on LPC/eSPI bus.) In order to prevent this situation, the CL checks TO_STS bit of ITCTS in these routines. If this bit is set, restoring ITIM32 preload counter value to maximum value and processing overflow will be done by force_time(). BRANCH=eve,fizz,poppy BUG=b:76182199 TEST=No build errors for npcx series. Passed test command of CL 979389 on npcx_evb. No symptom occurred during warm reset stress test on soraka. Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/979874 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* NPCX-specific hwtimer module for Chrome EC */
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#ifndef __CROS_EC_HWTIMER_CHIP_H
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#define __CROS_EC_HWTIMER_CHIP_H
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/* Channel definition for ITIM */
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#define ITIM_EVENT_NO ITIM16_1
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#define ITIM_WDG_NO ITIM16_5
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/* Use ITIM32 as main hardware timer */
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#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF
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/* Maximum deadline of event */
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#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT
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/* Clock source for ITIM16 */
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enum ITIM_SOURCE_CLOCK_T {
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ITIM_SOURCE_CLOCK_APB2 = 0,
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ITIM_SOURCE_CLOCK_32K = 1,
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};
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/* Initialize ITIM16 timer */
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void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source);
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/* Returns the counter value of event timer */
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uint16_t __hw_clock_event_count(void);
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/* Returns time delay because of deep idle */
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uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt);
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/* Handle ITIM32 overflow if interrupt is disabled */
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void __hw_clock_handle_overflow(uint32_t clksrc_high);
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#endif /* __CROS_EC_HWTIMER_CHIP_H */
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