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7d94cf93ee
AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
420 lines
14 KiB
C
420 lines
14 KiB
C
/* $NoKeywords:$ */
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/**
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* @file
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*
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* Install of build option: Memory
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*
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* Contains AMD AGESA install macros and test conditions. Output is the
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* defaults tables reflecting the User's build options selection.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: Options
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* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
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*/
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/*****************************************************************************
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*
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* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
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*
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* AMD is granting you permission to use this software (the Materials)
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* pursuant to the terms and conditions of your Software License Agreement
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* with AMD. This header does *NOT* give you permission to use the Materials
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* or any rights under AMD's intellectual property. Your use of any portion
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* of these Materials shall constitute your acceptance of those terms and
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* conditions. If you do not agree to the terms and conditions of the Software
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* License Agreement, please do not use any portion of these Materials.
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*
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* CONFIDENTIALITY: The Materials and all other information, identified as
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* confidential and provided to you by AMD shall be kept confidential in
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* accordance with the terms and conditions of the Software License Agreement.
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*
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* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
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* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
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* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
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* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
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* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
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* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
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* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
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* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
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* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
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* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
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*
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* AMD does not assume any responsibility for any errors which may appear in
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* the Materials or any other related information provided to you by AMD, or
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* result from use of the Materials or any related information.
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*
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* You agree that you will not reverse engineer or decompile the Materials.
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*
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* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
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* further information, software, technical information, know-how, or show-how
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* available to you. Additionally, AMD retains the right to modify the
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* Materials at any time, without notice, and is not obligated to provide such
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* modified Materials to you.
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*
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* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
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* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
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* subject to the restrictions as set forth in FAR 52.227-14 and
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* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
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* Government constitutes acknowledgement of AMD's proprietary rights in them.
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*
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* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
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* direct product thereof will be exported directly or indirectly, into any
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* country prohibited by the United States Export Administration Act and the
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* regulations thereunder, without the required authorization from the U.S.
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* government nor will be used for any purpose prohibited by the same.
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*
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***************************************************************************/
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#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
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#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
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#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
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#if (OPTION_MEMCTLR_DR == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
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#define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
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#else
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#define MEM_REC_NB_SUPPORT_DR
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#endif
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#if (OPTION_MEMCTLR_RB == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
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#define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
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#else
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#define MEM_REC_NB_SUPPORT_RB
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#endif
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#if (OPTION_MEMCTLR_DA == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
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#define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
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#else
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#define MEM_REC_NB_SUPPORT_DA
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#endif
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#if (OPTION_MEMCTLR_NI == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
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#define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
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#else
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#define MEM_REC_NB_SUPPORT_NI
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#endif
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#if (OPTION_MEMCTLR_PH == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
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#define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
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#else
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#define MEM_REC_NB_SUPPORT_PH
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#endif
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#if (OPTION_MEMCTLR_HY == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
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#define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
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#else
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#define MEM_REC_NB_SUPPORT_HY
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#endif
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#if (OPTION_MEMCTLR_C32 == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
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#define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
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#else
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#define MEM_REC_NB_SUPPORT_C32
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#endif
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#if (OPTION_MEMCTLR_LN == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
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#define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
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#else
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#define MEM_REC_NB_SUPPORT_LN
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#endif
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#if (OPTION_MEMCTLR_OR == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockOr;
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#define MEM_REC_NB_SUPPORT_OR MemRecConstructNBBlockOr,
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#else
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#define MEM_REC_NB_SUPPORT_OR
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#endif
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#if (OPTION_MEMCTLR_ON == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
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#define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
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#else
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#define MEM_REC_NB_SUPPORT_ON
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#endif
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#if (OPTION_MEMCTLR_TN == TRUE)
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extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockTN;
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#define MEM_REC_NB_SUPPORT_TN MemRecConstructNBBlockTN,
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#else
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#define MEM_REC_NB_SUPPORT_TN
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#endif
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MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
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MEM_REC_NB_SUPPORT_DR
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MEM_REC_NB_SUPPORT_RB
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MEM_REC_NB_SUPPORT_DA
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MEM_REC_NB_SUPPORT_PH
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MEM_REC_NB_SUPPORT_HY
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MEM_REC_NB_SUPPORT_C32
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MEM_REC_NB_SUPPORT_LN
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MEM_REC_NB_SUPPORT_OR
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MEM_REC_NB_SUPPORT_ON
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MEM_REC_NB_SUPPORT_NI
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MEM_REC_NB_SUPPORT_TN
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NULL
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};
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#define MEM_REC_TECH_CONSTRUCTOR_DDR2
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#if (OPTION_DDR3 == TRUE)
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extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
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#define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
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#else
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#define MEM_REC_TECH_CONSTRUCTOR_DDR3
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#endif
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MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
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MEM_REC_TECH_CONSTRUCTOR_DDR3
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MEM_REC_TECH_CONSTRUCTOR_DDR2
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NULL
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};
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#if OPTION_MEMCTLR_DR
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#define PSC_REC_DR_UDIMM_DDR2
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#define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
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#define PSC_REC_DR_RDIMM_DDR2
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#define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
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#define PSC_REC_DR_SODIMM_DDR2
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#define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
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#endif
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#if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
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#define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
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#define PSC_REC_DA_SODIMM_DDR2
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#define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
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#endif
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#if OPTION_MEMCTLR_HY
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#define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
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#define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
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#endif
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#if OPTION_MEMCTLR_C32
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#define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
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#define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
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#endif
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#if OPTION_MEMCTLR_OR
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#define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR,
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#define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR,
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#endif
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#if OPTION_MEMCTLR_TN
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#define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR,
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#define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR,
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#endif
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#ifndef PSC_REC_DR_UDIMM_DDR2
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#define PSC_REC_DR_UDIMM_DDR2
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#endif
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#ifndef PSC_REC_DR_UDIMM_DDR3
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#define PSC_REC_DR_UDIMM_DDR3
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#endif
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#ifndef PSC_REC_DR_RDIMM_DDR2
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#define PSC_REC_DR_RDIMM_DDR2
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#endif
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#ifndef PSC_REC_DR_RDIMM_DDR3
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#define PSC_REC_DR_RDIMM_DDR3
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#endif
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#ifndef PSC_REC_DR_SODIMM_DDR2
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#define PSC_REC_DR_SODIMM_DDR2
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#endif
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#ifndef PSC_REC_DR_SODIMM_DDR3
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#define PSC_REC_DR_SODIMM_DDR3
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#endif
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#ifndef PSC_REC_DA_UDIMM_DDR3
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#define PSC_REC_DA_UDIMM_DDR3
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#endif
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#ifndef PSC_REC_DA_SODIMM_DDR2
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#define PSC_REC_DA_SODIMM_DDR2
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#endif
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#ifndef PSC_REC_DA_SODIMM_DDR3
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#define PSC_REC_DA_SODIMM_DDR3
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#endif
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#ifndef PSC_REC_HY_UDIMM_DDR3
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#define PSC_REC_HY_UDIMM_DDR3
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#endif
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#ifndef PSC_REC_HY_RDIMM_DDR3
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#define PSC_REC_HY_RDIMM_DDR3
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#endif
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#ifndef PSC_REC_C32_UDIMM_DDR3
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#define PSC_REC_C32_UDIMM_DDR3
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#endif
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#ifndef PSC_REC_C32_RDIMM_DDR3
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#define PSC_REC_C32_RDIMM_DDR3
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#endif
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#ifndef PSC_REC_OR_UDIMM_DDR3
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#define PSC_REC_OR_UDIMM_DDR3
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#endif
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#ifndef PSC_REC_OR_RDIMM_DDR3
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#define PSC_REC_OR_RDIMM_DDR3
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#endif
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MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
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PSC_REC_DR_UDIMM_DDR2
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PSC_REC_DR_RDIMM_DDR2
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PSC_REC_DR_SODIMM_DDR2
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PSC_REC_DR_UDIMM_DDR3
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PSC_REC_DR_RDIMM_DDR3
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PSC_REC_DR_SODIMM_DDR3
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PSC_REC_DA_SODIMM_DDR2
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PSC_REC_DA_UDIMM_DDR3
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PSC_REC_DA_SODIMM_DDR3
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PSC_REC_HY_UDIMM_DDR3
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PSC_REC_HY_RDIMM_DDR3
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PSC_REC_C32_UDIMM_DDR3
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PSC_REC_C32_RDIMM_DDR3
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PSC_REC_OR_UDIMM_DDR3
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PSC_REC_OR_RDIMM_DDR3
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NULL
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};
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/*---------------------------------------------------------------------------------------------------
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* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
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*
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*
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*---------------------------------------------------------------------------------------------------
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*/
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#define MEM_PSC_REC_FLOW_BLOCK_END NULL
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#define PSC_REC_TBL_END NULL
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#define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) MemRecDefTrue
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#if OPTION_MEMCTLR_TN
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#if OPTION_UDIMMS
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extern PSC_TBL_ENTRY RecTNDramTermTblEntU;
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#define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM &RecTNDramTermTblEntU,
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extern PSC_TBL_ENTRY RecTNSAOTblEntU3;
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#define PSC_REC_TBL_TN_UDIMM3_SAO &RecTNSAOTblEntU3,
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#endif
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#if OPTION_SODIMMS
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extern PSC_TBL_ENTRY RecTNSAOTblEntSO3;
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#define PSC_REC_TBL_TN_SODIMM3_SAO &RecTNSAOTblEntSO3,
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extern PSC_TBL_ENTRY RecTNDramTermTblEntSO;
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#define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM &RecTNDramTermTblEntSO,
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#endif
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extern PSC_TBL_ENTRY RecTNMR0WrTblEntry;
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extern PSC_TBL_ENTRY RecTNMR0CLTblEntry;
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extern PSC_TBL_ENTRY RecTNDdr3CKETriEnt;
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extern PSC_TBL_ENTRY RecTNOdtPatTblEnt;
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#ifndef PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
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#define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
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#endif
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#ifndef PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
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#define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
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#endif
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#ifndef PSC_REC_TBL_TN_SODIMM3_SAO
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#define PSC_REC_TBL_TN_SODIMM3_SAO
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#endif
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#ifndef PSC_REC_TBL_TN_UDIMM3_SAO
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#define PSC_REC_TBL_TN_UDIMM3_SAO
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#endif
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PSC_TBL_ENTRY* memRecPSCTblDramTermArrayTN[] = {
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PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
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PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
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PSC_REC_TBL_END
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};
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PSC_TBL_ENTRY* memRecPSCTblODTPatArrayTN[] = {
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&RecTNOdtPatTblEnt,
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PSC_REC_TBL_END
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};
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PSC_TBL_ENTRY* memRecPSCTblSAOArrayTN[] = {
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PSC_REC_TBL_TN_SODIMM3_SAO
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PSC_REC_TBL_TN_UDIMM3_SAO
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PSC_REC_TBL_END
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};
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PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayTN[] = {
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&RecTNMR0WrTblEntry,
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PSC_REC_TBL_END
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};
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PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayTN[] = {
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&RecTNMR0CLTblEntry,
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PSC_REC_TBL_END
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};
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MEM_PSC_TABLE_BLOCK memRecPSCTblBlockTN = {
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NULL,
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(PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayTN,
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(PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayTN,
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(PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayTN,
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(PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayTN,
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(PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayTN,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL
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};
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extern MEM_PSC_FLOW MemPRecGetRttNomWr;
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#define PSC_REC_FLOW_TN_DRAM_TERM MemPRecGetRttNomWr
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extern MEM_PSC_FLOW MemPRecGetODTPattern;
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#define PSC_REC_FLOW_TN_ODT_PATTERN MemPRecGetODTPattern
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extern MEM_PSC_FLOW MemPRecGetSAO;
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#define PSC_REC_FLOW_TN_SAO MemPRecGetSAO
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extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
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#define PSC_REC_FLOW_TN_MR0_WRCL MemPRecGetMR0WrCL
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MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowTN = {
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&memRecPSCTblBlockTN,
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MEM_REC_PSC_FLOW_DEFTRUE,
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PSC_REC_FLOW_TN_DRAM_TERM,
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PSC_REC_FLOW_TN_ODT_PATTERN,
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PSC_REC_FLOW_TN_SAO,
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PSC_REC_FLOW_TN_MR0_WRCL,
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MEM_REC_PSC_FLOW_DEFTRUE,
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MEM_REC_PSC_FLOW_DEFTRUE,
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MEM_REC_PSC_FLOW_DEFTRUE,
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MEM_REC_PSC_FLOW_DEFTRUE,
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MEM_REC_PSC_FLOW_DEFTRUE,
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MEM_REC_PSC_FLOW_DEFTRUE
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};
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#define MEM_PSC_REC_FLOW_BLOCK_TN &memRecPlatSpecFlowTN,
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#else
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#define MEM_PSC_REC_FLOW_BLOCK_TN
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#endif
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MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
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MEM_PSC_REC_FLOW_BLOCK_TN
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MEM_PSC_REC_FLOW_BLOCK_END
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};
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#else
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/*---------------------------------------------------------------------------------------------------
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* DEFAULT TECHNOLOGY BLOCK
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*
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*
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*---------------------------------------------------------------------------------------------------
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*/
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MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed
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NULL
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};
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/*---------------------------------------------------------------------------------------------------
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* DEFAULT NORTHBRIDGE SUPPORT LIST
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*
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*
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*---------------------------------------------------------------------------------------------------
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*/
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MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
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NULL
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};
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/*----------------------------------------------------------------------
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* DEFAULT PSCFG DEFINITIONS
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*
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*----------------------------------------------------------------------
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*/
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MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
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NULL
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};
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/*----------------------------------------------------------------------
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* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
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*
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*----------------------------------------------------------------------
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*/
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MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
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NULL
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};
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#endif
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#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_
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