mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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7e61e45402
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SET_NB_CFG_54
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#define SET_NB_CFG_54 1
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#endif
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#include "cpu/amd/quadcore/quadcore_id.c"
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static inline u32 get_core_num_in_bsp(u32 nodeid)
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{
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u32 dword;
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dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
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dword >>= 12;
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dword &= 3;
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return dword;
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}
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#if SET_NB_CFG_54 == 1
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static inline u8 set_apicid_cpuid_lo(void)
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{
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// set the NB_CFG[54]=1; why the OS will be happy with that ???
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msr_t msr;
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msr = rdmsr(NB_CFG_MSR);
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msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
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wrmsr(NB_CFG_MSR, msr);
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return 1;
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}
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#else
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static inline void set_apicid_cpuid_lo(void) { }
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#endif
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static inline void real_start_other_core(u32 nodeid, u32 cores)
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{
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u32 dword;
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printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
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/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
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accesses and error logging to core0 */
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dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
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dword |= 1 << 27; // NbMcaToMstCpuEn bit
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pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
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// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
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dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
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dword |= 1 << 5;
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pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
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if(cores > 1) {
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dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
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dword |= (1 << 0); // core2
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if(cores > 2) { // core3
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dword |= (1 << 1);
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}
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pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
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}
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}
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//it is running on core0 of node0
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static inline void start_other_cores(void)
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{
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u32 nodes;
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u32 nodeid;
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// disable quad_core
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if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) {
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printk_debug("Skip additional core init\n");
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return;
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}
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nodes = get_nodes();
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for (nodeid = 0; nodeid < nodes; nodeid++) {
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u32 cores = get_core_num_in_bsp(nodeid);
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printk_debug("init node: %02x cores: %02x \n", nodeid, cores);
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if (cores > 0) {
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real_start_other_core(nodeid, cores);
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}
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}
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}
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