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Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
146 lines
3.9 KiB
C
146 lines
3.9 KiB
C
/*
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* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include <stddef.h>
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#include "common.h"
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#include "version.h"
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/* FMAP structs. See http://code.google.com/p/flashmap/wiki/FmapSpec */
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#define FMAP_NAMELEN 32
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#define FMAP_SIGNATURE "__FMAP__"
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#define FMAP_SIGNATURE_SIZE 8
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#define FMAP_VER_MAJOR 1
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#define FMAP_VER_MINOR 0
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/*
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* For address containing CONFIG_FLASH_BASE (symbols in *.RO.lds.S and
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* variable), this computes the offset to the start of the image on flash.
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*/
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#ifdef NPCX_RO_HEADER
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#define RELATIVE_RO(addr) ((addr) - CONFIG_CDRAM_BASE)
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#else
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#define RELATIVE_RO(addr) ((addr) - CONFIG_FLASH_BASE - CONFIG_RO_MEM_OFF)
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#endif
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struct fmap_header {
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char fmap_signature[FMAP_SIGNATURE_SIZE];
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uint8_t fmap_ver_major;
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uint8_t fmap_ver_minor;
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uint64_t fmap_base;
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uint32_t fmap_size;
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char fmap_name[FMAP_NAMELEN];
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uint16_t fmap_nareas;
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} __packed;
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#define FMAP_AREA_STATIC (1 << 0) /* can be checksummed */
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#define FMAP_AREA_COMPRESSED (1 << 1) /* may be compressed */
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#define FMAP_AREA_RO (1 << 2) /* writes may fail */
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struct fmap_area_header {
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uint32_t area_offset;
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uint32_t area_size;
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char area_name[FMAP_NAMELEN];
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uint16_t area_flags;
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} __packed;
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#define NUM_EC_FMAP_AREAS 7
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const struct _ec_fmap {
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struct fmap_header header;
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struct fmap_area_header area[NUM_EC_FMAP_AREAS];
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} ec_fmap __attribute__((section(".google"))) = {
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/* Header */
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{
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.fmap_signature = {'_', '_', 'F', 'M', 'A', 'P', '_', '_'},
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.fmap_ver_major = FMAP_VER_MAJOR,
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.fmap_ver_minor = FMAP_VER_MINOR,
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.fmap_base = CONFIG_FLASH_BASE,
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.fmap_size = CONFIG_FLASH_SIZE,
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.fmap_name = "EC_FMAP",
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.fmap_nareas = NUM_EC_FMAP_AREAS,
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},
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{
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/* RO Firmware */
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{
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/*
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* Range of RO firmware to be updated. Verified in
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* factory finalization by hash. Should not have
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* volatile data (ex, calibration results).
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*/
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.area_name = "EC_RO",
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.area_offset = CONFIG_RO_STORAGE_OFF,
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.area_size = CONFIG_RO_SIZE,
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.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
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},
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{
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/* (Optional) RO firmware code. */
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.area_name = "FR_MAIN",
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.area_offset = CONFIG_RO_STORAGE_OFF,
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.area_size = CONFIG_RO_SIZE,
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.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
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},
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{
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/*
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* RO firmware version ID. Must be NULL terminated
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* ASCII, and padded with \0.
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*/
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.area_name = "RO_FRID",
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.area_offset = CONFIG_RO_STORAGE_OFF +
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RELATIVE_RO((uint32_t)__version_struct_offset) +
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offsetof(struct version_struct, version),
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.area_size = sizeof(version_data.version),
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.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
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},
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/* Other RO stuff: FMAP, WP, KEYS, etc. */
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{
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.area_name = "FMAP",
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.area_offset = CONFIG_RO_STORAGE_OFF +
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RELATIVE_RO((uint32_t)&ec_fmap),
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.area_size = sizeof(ec_fmap),
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.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
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},
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{
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/*
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* The range for write protection, for factory
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* finalization. Should include (may be identical to)
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* EC_RO and aligned to hardware specification.
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*/
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.area_name = "WP_RO",
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.area_offset = CONFIG_WP_OFF,
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.area_size = CONFIG_WP_SIZE,
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.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
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},
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/* RW Firmware */
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{
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/* The range of RW firmware to be auto-updated. */
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.area_name = "EC_RW",
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.area_offset = CONFIG_RW_STORAGE_OFF,
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.area_size = CONFIG_RW_SIZE,
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.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
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},
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{
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/*
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* RW firmware version ID. Must be NULL terminated
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* ASCII, and padded with \0.
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* TODO: Get the relative offset of
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* __version_struct_offset within our RW image to
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* accomodate image asymmetry.
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*/
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.area_name = "RW_FWID",
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.area_offset = CONFIG_RW_STORAGE_OFF +
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RELATIVE_RO((uint32_t)__version_struct_offset) +
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offsetof(struct version_struct, version),
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.area_size = sizeof(version_data.version),
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.area_flags = FMAP_AREA_STATIC,
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},
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}
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};
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