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In order to wake the chips from STOP/SLEEP mode with a touch, we need to put the two chips in correct state before going into STOP/SLEEP mode. Also, when one of the chips wakes up, it needs to wake the other chip with GPIO interrupt. This CL implements the necessary methods and also adds a sample routine that put the chips in STOP mode and wait for a touch using the implemented methods. BUG=None TEST=Build and boot. Touch the panel and see the response in console. BRANCH=None Change-Id: Ia5f7df8b550ee2459bcae1840f8a2717c8d947ce Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204482 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
193 lines
4.2 KiB
C
193 lines
4.2 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware initialization and common functions */
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#include "common.h"
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#include "cpu.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "touch_scan.h"
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#include "util.h"
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void hardware_clock_init(void)
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{
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/* Turn on HSE */
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if (!(STM32_RCC_CR & (1 << 17))) {
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/* Enable HSE */
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STM32_RCC_CR |= (1 << 18) | (1 << 16);
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/* Wait for HSE to be ready */
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while (!(STM32_RCC_CR & (1 << 17)))
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;
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}
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/* PLLSRC = HSE/2 = 8MHz, PLLMUL = x6 = 48MHz */
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STM32_RCC_CFGR = 0x00534000;
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/* Enable PLL */
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STM32_RCC_CR |= 1 << 24;
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/* Wait for PLL to be ready */
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while (!(STM32_RCC_CR & (1 << 25)))
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;
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/* switch SYSCLK to PLL */
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STM32_RCC_CFGR = 0x00534002;
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/* wait until the PLL is the clock source */
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while ((STM32_RCC_CFGR & 0xc) != 0x8)
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;
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}
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static void power_init(void)
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{
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/* enable ADC1, ADC2, PMSE, SPI1, GPA-GPI, AFIO */
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STM32_RCC_APB2ENR = 0x0000f7fd;
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/* enable TIM2, TIM3, PWR */
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STM32_RCC_APB1ENR = 0x10000003;
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/* enable DMA, SRAM */
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STM32_RCC_AHBENR = 0x000005;
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}
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/* GPIO setting helpers */
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#define OUT(n) (0x1 << ((n & 0x7) * 4))
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#define OUT50(n) (0x3 << ((n & 0x7) * 4))
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#define ANALOG(n) (0x0)
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#define FLOAT(n) (0x4 << ((n & 0x7) * 4))
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#define GP_OD(n) (0x5 << ((n & 0x7) * 4))
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#define AF_PP(n) (0x9 << ((n & 0x7) * 4))
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#define AF_OD(n) (0xd << ((n & 0x7) * 4))
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#define LOW(n) (1 << (n + 16))
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#define HIGH(n) (1 << n)
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#define INT(n) (1 << n)
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static void pins_init(void)
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{
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/*
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* Disable JTAG and SWD. We want JTDI for UART Tx and SWD pins for
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* touch scan.
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*/
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STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24))
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| (4 << 24);
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/*
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* Initial pin usage:
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* PA0: SPI_NSS - INPUT/INT_FALLING
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* PA1: N_CHG - INPUT
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* PA3: SPI_CLK - INPUT
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* PA4: SPI_MISO - INPUT
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* PA6: CS1 - OUTPUT/HIGH
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* PA7: SPI_MOSI - INPUT
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* PA9: USB_PU - OUTPUT/LOW
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* PA15: UART TX - OUTPUT/HIGH
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* PI1: SYNC1 - OUTPUT/LOW
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* PI2: SYNC2 - OUTPUT/LOW
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*/
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STM32_GPIO_CRL(GPIO_A) = FLOAT(0) | FLOAT(1) | FLOAT(3) | FLOAT(4) |
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OUT(6) | FLOAT(7);
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STM32_GPIO_CRH(GPIO_A) = OUT(9) | OUT(15);
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STM32_GPIO_BSRR(GPIO_A) = LOW(1) | HIGH(6) | LOW(9) | HIGH(15);
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STM32_EXTI_FTSR |= INT(0);
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STM32_GPIO_CRL(GPIO_I) = OUT(1) | OUT(2);
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STM32_GPIO_BSRR(GPIO_I) = LOW(1) | LOW(2);
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}
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static void adc_init(void)
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{
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int id;
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for (id = 0; id < 2; ++id) {
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/* Enable ADC clock */
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STM32_RCC_APB2ENR |= (1 << (14 + id));
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/* Power on ADC if it's off */
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if (!(STM32_ADC_CR2(id) & (1 << 0))) {
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/* Power on ADC module */
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STM32_ADC_CR2(id) |= (1 << 0); /* ADON */
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/* Reset calibration */
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STM32_ADC_CR2(id) |= (1 << 3); /* RSTCAL */
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while (STM32_ADC_CR2(id) & (1 << 3))
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;
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/* A/D Calibrate */
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STM32_ADC_CR2(id) |= (1 << 2); /* CAL */
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while (STM32_ADC_CR2(id) & (1 << 2))
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;
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}
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/* Set right alignment */
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STM32_ADC_CR2(id) &= ~(1 << 11);
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/* Set sampling time */
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STM32_ADC_SMPR2(id) = ADC_SMPR_VAL;
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/* Select AIN0 */
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STM32_ADC_SQR3(id) &= ~0x1f;
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/* Disable DMA */
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STM32_ADC_CR2(id) &= ~(1 << 8);
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/* Disable scan mode */
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STM32_ADC_CR1(id) &= ~(1 << 8);
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}
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}
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static void timers_init(void)
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{
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STM32_TIM_CR1(3) = 0x0004; /* MSB */
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STM32_TIM_CR1(2) = 0x0004; /* LSB */
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STM32_TIM_CR2(3) = 0x0000;
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STM32_TIM_CR2(2) = 0x0020;
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STM32_TIM_SMCR(3) = 0x0007 | (1 << 4);
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STM32_TIM_SMCR(2) = 0x0000;
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STM32_TIM_ARR(3) = 0xffff;
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STM32_TIM_ARR(2) = 0xffff;
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STM32_TIM_PSC(3) = 0;
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STM32_TIM_PSC(2) = CPU_CLOCK / 1000000 - 1;
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STM32_TIM_EGR(3) = 0x0001;
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STM32_TIM_EGR(2) = 0x0001;
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STM32_TIM_DIER(3) = 0x0001;
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STM32_TIM_DIER(2) = 0x0000;
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STM32_TIM_CR1(3) |= 1;
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STM32_TIM_CR1(2) |= 1;
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STM32_TIM_CNT(3) = 0;
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STM32_TIM_CNT(2) = 0;
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task_enable_irq(STM32_IRQ_TIM3);
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task_enable_irq(STM32_IRQ_TIM2);
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}
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static void irq_init(void)
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{
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/* clear all pending interrupts */
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CPU_NVIC_UNPEND(0) = 0xffffffff;
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/* enable global interrupts */
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asm("cpsie i");
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}
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static void pmse_init(void)
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{
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/* Use 10K-ohm pull down */
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STM32_PMSE_CR |= (1 << 13);
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}
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void hardware_init(void)
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{
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power_init();
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hardware_clock_init();
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pins_init();
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timers_init();
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adc_init();
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irq_init();
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pmse_init();
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}
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