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https://github.com/Telecominfraproject/OpenCellular.git
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5d4846ee52
When the cable flip button is pressed, instead of only flipping on Plankton side, we should also signal the port partner to flip. This is done by sending a custom VDM. Upon receiving the flip VDM, the port partner is responsible of flipping the DP/USB polarity. Note that the "flip" here only affects the superspeed lanes. The CC lines polarity is not changed. We need this for factory test automation, and this "flip" function should only be used for testing purpose as it clearly violates the USB PD spec and it only works on devices that accept the custom flip VDM. BRANCH=Samus BUG=chrome-os-partner:32163 TEST=COnnect Plankton and Ryu. Press the button on Plankton and make sure the polarity GPIOs on Ryu are negated. Change-Id: I7ee5ea70067de4f422a7478623fe7fe8d3724372 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/223325 Reviewed-by: Alec Berg <alecaberg@chromium.org>
117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* ryu board configuration */
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#ifndef __BOARD_H
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#define __BOARD_H
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/* 48 MHz SYSCLK clock frequency */
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#define CPU_CLOCK 48000000
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/* the UART console is on USART2 (PA14/PA15) */
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#undef CONFIG_UART_CONSOLE
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#define CONFIG_UART_CONSOLE 2
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/* By default, enable all console messages excepted USB */
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#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USBPD))
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/* Optional features */
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#define CONFIG_STM_HWTIMER32
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#define CONFIG_USB_POWER_DELIVERY
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#define CONFIG_USB_PD_CUSTOM_VDM
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#define CONFIG_USB_PD_DUAL_ROLE
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#define CONFIG_USB_PD_FLASH_ERASE_CHECK
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#define CONFIG_USB_PD_INTERNAL_COMP
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#define CONFIG_USBC_SS_MUX
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#define CONFIG_USBC_VCONN
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#define CONFIG_ADC
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#define CONFIG_HW_CRC
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#define CONFIG_I2C
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#undef CONFIG_LID_SWITCH
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#define CONFIG_VBOOT_HASH
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#undef CONFIG_WATCHDOG_HELP
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#undef CONFIG_TASK_PROFILING
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#undef CONFIG_CONSOLE_CMDHELP
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#define CONFIG_INDUCTIVE_CHARGING
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#undef CONFIG_HIBERNATE
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#define CONFIG_DEBUG_ASSERT_BRIEF
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/* Disable unused console command to save flash space */
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#undef CONFIG_CMD_POWERINDEBUG
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/*
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* Pericom I2C workaround
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* TODO(crosbug.com/p/31529): Remove this.
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*/
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#define CONFIG_I2C_SCL_GATE_PORT I2C_PORT_MASTER
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#define CONFIG_I2C_SCL_GATE_ADDR 0x4a
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#define CONFIG_I2C_SCL_GATE_GPIO GPIO_PERICOM_CLK_EN
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/* Charging/Power configuration */
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#undef CONFIG_BATTERY_RYU /* TODO implement */
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#define CONFIG_BATTERY_BQ27541
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#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
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#define CONFIG_BATTERY_REVIVE_DISCONNECT
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#define CONFIG_CHARGER
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#define CONFIG_CHARGER_V2
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#define CONFIG_CHARGER_BQ24773
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#define CONFIG_CHARGER_ILIM_PIN_DISABLED
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#define CONFIG_CHARGER_SENSE_RESISTOR 5
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#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
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#define CONFIG_CHARGER_INPUT_CURRENT 512
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#define CONFIG_CHARGER_DISCHARGE_ON_AC
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#define CONFIG_CHIPSET_TEGRA
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#define CONFIG_PMIC_FW_LONG_PRESS_TIMER
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#define CONFIG_POWER_COMMON
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#define CONFIG_POWER_BUTTON
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#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1
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/* I2C ports configuration */
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#define I2C_PORT_MASTER 0
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#define I2C_PORT_SLAVE 1
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#define I2C_PORT_EC I2C_PORT_SLAVE
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#define I2C_PORT_CHARGER I2C_PORT_MASTER
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#define I2C_PORT_BATTERY I2C_PORT_MASTER
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/* slave address for host commands */
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#ifdef HAS_TASK_HOSTCMD
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#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3c
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#endif
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#ifndef __ASSEMBLER__
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/* Timer selection */
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#define TIM_CLOCK32 2
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#define TIM_ADC 3
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#include "gpio_signal.h"
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enum power_signal {
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TEGRA_XPSHOLD = 0,
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TEGRA_SUSPEND_ASSERTED,
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/* Number of power signals */
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POWER_SIGNAL_COUNT
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};
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/* ADC signal */
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enum adc_channel {
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ADC_VBUS = 0,
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ADC_CC1_PD,
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ADC_CC2_PD,
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ADC_IADP,
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ADC_IBAT,
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/* Number of ADC channels */
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ADC_CH_COUNT
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};
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/* Discharge battery when on AC power for factory test. */
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int board_discharge_on_ac(int enable);
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#endif /* !__ASSEMBLER__ */
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#endif /* __BOARD_H */
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