Roberto Vargas 8fd307ffd6 Flush the affinity data in psci_affinity_info ...

There is an edge case where the cache maintaince done in
psci_do_cpu_off may not seen by some cores. This case is handled in
psci_cpu_on_start but it hasn't handled in psci_affinity_info.

Change-Id: I4d64f3d1ca9528e364aea8d04e2d254f201e1702
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

2017-11-20 13:38:43 +00:00

..

aarch32

Exit early if size zero for cache helpers

2017-06-21 17:46:28 +01:00

aarch64

Introduce functions to disable the MMU in EL1

2017-10-17 12:02:37 +01:00

compiler-rt

Import ctzdi2.c from LLVM compiler-rt

2017-07-26 09:28:23 +01:00

cpus

Cortex-A72: Implement workaround for erratum 859971

2017-09-07 14:22:02 +01:00

el3_runtime

Move FPEXC32_EL2 to FP Context

2017-11-15 22:42:05 +00:00

libfdt

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

locks

Add macro to test for minimum architecture version

2017-08-24 17:23:43 +01:00

optee

Add Trusted OS extra image parsing support for ARM standard platforms

2017-08-09 18:06:05 +08:00

pmf

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

psci

Flush the affinity data in psci_affinity_info

2017-11-20 13:38:43 +00:00

semihosting

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

stack_protector

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

stdlib

Use standard UNIX file:line format in assert

2017-07-19 05:57:40 +01:00

utils

Add mem_region utility functions

2017-09-25 13:32:20 +01:00

xlat_tables

Set TCR_EL1.EPD1 bit to 1

2017-09-21 11:57:11 +01:00

xlat_tables_v2

xlat: Make function to calculate TCR PA bits public

2017-11-08 18:05:14 +00:00