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91089f360a
The FPEXC32_EL2 register controls SIMD and FP functionality when the lower ELs are executing in AArch32 mode. It is architecturally mapped to AArch32 system register FPEXC. This patch removes FPEXC32_EL2 register from the System Register context and adds it to the floating-point context. EL3 only saves / restores the floating-point context if the build option CTX_INCLUDE_FPREGS is set to 1. The rationale for this change is that if the Secure world is using FP functionality and EL3 is not managing the FP context, then the Secure world will save / restore the appropriate FP registers. NOTE - this is a break in behaviour in the unlikely case that CTX_INCLUDE_FPREGS is set to 0 and the platform contains an AArch32 Secure Payload that modifies FPEXC, but does not save and restore this register Change-Id: Iab80abcbfe302752d52b323b4abcc334b585c184 Signed-off-by: David Cunado <david.cunado@arm.com>
334 lines
12 KiB
C
334 lines
12 KiB
C
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CONTEXT_H__
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#define __CONTEXT_H__
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'gp_regs'
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* structure at their correct offsets.
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******************************************************************************/
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#define CTX_GPREGS_OFFSET U(0x0)
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#define CTX_GPREG_X0 U(0x0)
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#define CTX_GPREG_X1 U(0x8)
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#define CTX_GPREG_X2 U(0x10)
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#define CTX_GPREG_X3 U(0x18)
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#define CTX_GPREG_X4 U(0x20)
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#define CTX_GPREG_X5 U(0x28)
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#define CTX_GPREG_X6 U(0x30)
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#define CTX_GPREG_X7 U(0x38)
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#define CTX_GPREG_X8 U(0x40)
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#define CTX_GPREG_X9 U(0x48)
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#define CTX_GPREG_X10 U(0x50)
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#define CTX_GPREG_X11 U(0x58)
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#define CTX_GPREG_X12 U(0x60)
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#define CTX_GPREG_X13 U(0x68)
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#define CTX_GPREG_X14 U(0x70)
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#define CTX_GPREG_X15 U(0x78)
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#define CTX_GPREG_X16 U(0x80)
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#define CTX_GPREG_X17 U(0x88)
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#define CTX_GPREG_X18 U(0x90)
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#define CTX_GPREG_X19 U(0x98)
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#define CTX_GPREG_X20 U(0xa0)
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#define CTX_GPREG_X21 U(0xa8)
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#define CTX_GPREG_X22 U(0xb0)
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#define CTX_GPREG_X23 U(0xb8)
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#define CTX_GPREG_X24 U(0xc0)
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#define CTX_GPREG_X25 U(0xc8)
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#define CTX_GPREG_X26 U(0xd0)
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#define CTX_GPREG_X27 U(0xd8)
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#define CTX_GPREG_X28 U(0xe0)
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#define CTX_GPREG_X29 U(0xe8)
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#define CTX_GPREG_LR U(0xf0)
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#define CTX_GPREG_SP_EL0 U(0xf8)
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#define CTX_GPREGS_END U(0x100)
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'el3_state'
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* structure at their correct offsets. Note that some of the registers are only
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* 32-bits wide but are stored as 64-bit values for convenience
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******************************************************************************/
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#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
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#define CTX_SCR_EL3 U(0x0)
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#define CTX_RUNTIME_SP U(0x8)
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#define CTX_SPSR_EL3 U(0x10)
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#define CTX_ELR_EL3 U(0x18)
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#define CTX_EL3STATE_END U(0x20)
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the
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* 'el1_sys_regs' structure at their correct offsets. Note that some of the
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* registers are only 32-bits wide but are stored as 64-bit values for
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* convenience
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******************************************************************************/
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#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
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#define CTX_SPSR_EL1 U(0x0)
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#define CTX_ELR_EL1 U(0x8)
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#define CTX_SCTLR_EL1 U(0x10)
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#define CTX_ACTLR_EL1 U(0x18)
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#define CTX_CPACR_EL1 U(0x20)
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#define CTX_CSSELR_EL1 U(0x28)
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#define CTX_SP_EL1 U(0x30)
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#define CTX_ESR_EL1 U(0x38)
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#define CTX_TTBR0_EL1 U(0x40)
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#define CTX_TTBR1_EL1 U(0x48)
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#define CTX_MAIR_EL1 U(0x50)
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#define CTX_AMAIR_EL1 U(0x58)
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#define CTX_TCR_EL1 U(0x60)
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#define CTX_TPIDR_EL1 U(0x68)
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#define CTX_TPIDR_EL0 U(0x70)
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#define CTX_TPIDRRO_EL0 U(0x78)
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#define CTX_PAR_EL1 U(0x80)
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#define CTX_FAR_EL1 U(0x88)
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#define CTX_AFSR0_EL1 U(0x90)
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#define CTX_AFSR1_EL1 U(0x98)
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#define CTX_CONTEXTIDR_EL1 U(0xa0)
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#define CTX_VBAR_EL1 U(0xa8)
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#define CTX_PMCR_EL0 U(0xb0)
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/*
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* If the platform is AArch64-only, there is no need to save and restore these
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* AArch32 registers.
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*/
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#if CTX_INCLUDE_AARCH32_REGS
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#define CTX_SPSR_ABT U(0xc0) /* Align to the next 16 byte boundary */
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#define CTX_SPSR_UND U(0xc8)
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#define CTX_SPSR_IRQ U(0xd0)
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#define CTX_SPSR_FIQ U(0xd8)
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#define CTX_DACR32_EL2 U(0xe0)
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#define CTX_IFSR32_EL2 U(0xe8)
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#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */
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#else
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#define CTX_TIMER_SYSREGS_OFF U(0xc0) /* Align to the next 16 byte boundary */
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#endif /* __CTX_INCLUDE_AARCH32_REGS__ */
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/*
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* If the timer registers aren't saved and restored, we don't have to reserve
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* space for them in the context
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*/
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#if NS_TIMER_SWITCH
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#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0))
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#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8))
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#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10))
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#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18))
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#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20))
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#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */
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#else
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#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF
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#endif /* __NS_TIMER_SWITCH__ */
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'fp_regs'
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* structure at their correct offsets.
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******************************************************************************/
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#if CTX_INCLUDE_FPREGS
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#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
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#define CTX_FP_Q0 U(0x0)
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#define CTX_FP_Q1 U(0x10)
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#define CTX_FP_Q2 U(0x20)
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#define CTX_FP_Q3 U(0x30)
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#define CTX_FP_Q4 U(0x40)
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#define CTX_FP_Q5 U(0x50)
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#define CTX_FP_Q6 U(0x60)
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#define CTX_FP_Q7 U(0x70)
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#define CTX_FP_Q8 U(0x80)
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#define CTX_FP_Q9 U(0x90)
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#define CTX_FP_Q10 U(0xa0)
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#define CTX_FP_Q11 U(0xb0)
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#define CTX_FP_Q12 U(0xc0)
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#define CTX_FP_Q13 U(0xd0)
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#define CTX_FP_Q14 U(0xe0)
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#define CTX_FP_Q15 U(0xf0)
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#define CTX_FP_Q16 U(0x100)
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#define CTX_FP_Q17 U(0x110)
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#define CTX_FP_Q18 U(0x120)
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#define CTX_FP_Q19 U(0x130)
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#define CTX_FP_Q20 U(0x140)
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#define CTX_FP_Q21 U(0x150)
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#define CTX_FP_Q22 U(0x160)
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#define CTX_FP_Q23 U(0x170)
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#define CTX_FP_Q24 U(0x180)
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#define CTX_FP_Q25 U(0x190)
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#define CTX_FP_Q26 U(0x1a0)
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#define CTX_FP_Q27 U(0x1b0)
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#define CTX_FP_Q28 U(0x1c0)
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#define CTX_FP_Q29 U(0x1d0)
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#define CTX_FP_Q30 U(0x1e0)
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#define CTX_FP_Q31 U(0x1f0)
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#define CTX_FP_FPSR U(0x200)
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#define CTX_FP_FPCR U(0x208)
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#if CTX_INCLUDE_AARCH32_REGS
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#define CTX_FP_FPEXC32_EL2 U(0x210)
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#define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */
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#else
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#define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */
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#endif
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#endif
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */
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#include <stdint.h>
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/*
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* Common constants to help define the 'cpu_context' structure and its
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* members below.
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*/
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#define DWORD_SHIFT U(3)
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#define DEFINE_REG_STRUCT(name, num_regs) \
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typedef struct name { \
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uint64_t _regs[num_regs]; \
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} __aligned(16) name##_t
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/* Constants to determine the size of individual context structures */
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#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
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#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT)
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#if CTX_INCLUDE_FPREGS
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#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
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#endif
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#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
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/*
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* AArch64 general purpose register context structure. Usually x0-x18,
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* lr are saved as the compiler is expected to preserve the remaining
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* callee saved registers if used by the C runtime and the assembler
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* does not touch the remaining. But in case of world switch during
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* exception handling, we need to save the callee registers too.
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*/
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DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
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/*
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* AArch64 EL1 system register context structure for preserving the
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* architectural state during switches from one security state to
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* another in EL1.
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*/
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DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL);
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/*
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* AArch64 floating point register context structure for preserving
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* the floating point state during switches from one security state to
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* another.
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*/
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#if CTX_INCLUDE_FPREGS
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DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL);
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#endif
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/*
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* Miscellaneous registers used by EL3 firmware to maintain its state
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* across exception entries and exits
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*/
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DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
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/*
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* Macros to access members of any of the above structures using their
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* offsets
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*/
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#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT])
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#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \
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= val)
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/*
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* Top-level context structure which is used by EL3 firmware to
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* preserve the state of a core at EL1 in one of the two security
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* states and save enough EL3 meta data to be able to return to that
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* EL and security state. The context management library will be used
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* to ensure that SP_EL3 always points to an instance of this
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* structure at exception entry and exit. Each instance will
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* correspond to either the secure or the non-secure state.
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*/
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typedef struct cpu_context {
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gp_regs_t gpregs_ctx;
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el3_state_t el3state_ctx;
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el1_sys_regs_t sysregs_ctx;
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#if CTX_INCLUDE_FPREGS
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fp_regs_t fpregs_ctx;
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#endif
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} cpu_context_t;
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/* Macros to access members of the 'cpu_context_t' structure */
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#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
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#if CTX_INCLUDE_FPREGS
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#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx)
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#endif
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#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx)
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#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
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/*
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* Compile time assertions related to the 'cpu_context' structure to
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* ensure that the assembler and the compiler view of the offsets of
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* the structure members is the same.
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*/
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CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
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assert_core_context_gp_offset_mismatch);
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CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \
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assert_core_context_sys_offset_mismatch);
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#if CTX_INCLUDE_FPREGS
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CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
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assert_core_context_fp_offset_mismatch);
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#endif
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CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
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assert_core_context_el3state_offset_mismatch);
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/*
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* Helper macro to set the general purpose registers that correspond to
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* parameters in an aapcs_64 call i.e. x0-x7
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*/
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#define set_aapcs_args0(ctx, x0) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
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} while (0)
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#define set_aapcs_args1(ctx, x0, x1) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
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set_aapcs_args0(ctx, x0); \
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} while (0)
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#define set_aapcs_args2(ctx, x0, x1, x2) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
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set_aapcs_args1(ctx, x0, x1); \
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} while (0)
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#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
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set_aapcs_args2(ctx, x0, x1, x2); \
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} while (0)
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#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
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set_aapcs_args3(ctx, x0, x1, x2, x3); \
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} while (0)
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#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
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set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
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} while (0)
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#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
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set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
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} while (0)
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#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
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set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
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} while (0)
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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void el1_sysregs_context_save(el1_sys_regs_t *regs);
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void el1_sysregs_context_save_post_ops(void);
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void el1_sysregs_context_restore(el1_sys_regs_t *regs);
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#if CTX_INCLUDE_FPREGS
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void fpregs_context_save(fp_regs_t *regs);
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void fpregs_context_restore(fp_regs_t *regs);
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#endif
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#undef CTX_SYSREG_ALL
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#if CTX_INCLUDE_FPREGS
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#undef CTX_FPREG_ALL
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#endif
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#undef CTX_GPREG_ALL
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#undef CTX_EL3STATE_ALL
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#endif /* __ASSEMBLY__ */
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#endif /* __CONTEXT_H__ */
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