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9342bb62d7
This changes the ordering of rail/PMIC init slightly so that the 3.3V rail comes up before the PMIC, which follows the ordering in the PMIC datasheet for cold booting. The way we did it earlier was to avoid interrupt storms caused by powering the SoC's GPIO block with SLP signals before powering the PMIC. However the PMIC ignores the SLP signals when it's first enabled, so while the suprious interrupts were visible on the scope it's unlikely that the software was affected. OTOH, as Kevin pointed out in CL:358913 enabling the PMIC before the 3.3V causes a race condition whereby the PMIC may fault. BUG=chrome-os-partner:51323 BRANCH=none TEST=built and booted on EVT Signed-off-by: Rachel Nancollas <rachelsn@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I6eb734f0600daa5de0d970ce228cf3e7ec97d01d Reviewed-on: https://chromium-review.googlesource.com/372344 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>