Files
OpenCellular/core/nds32/cpu.c
Vincent Palatin 93cc00fde1 ite: Port OS layer to Andestar v3m architecture
This will be used to support ITE IT8380 chip which contains an Andes
N801 core.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:23574
TEST=make BOARD=it8380dev

Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce
Reviewed-on: https://chromium-review.googlesource.com/175480
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
2013-12-10 19:17:54 +00:00

53 lines
898 B
C

/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Set up the N8 core
*/
#include "cpu.h"
void cpu_init(void)
{
/* DLM initialization is done in init.S */
}
/**
* Count leading zeros
*
* @param x non null integer.
* @return the number of leading 0-bits in x,
* starting at the most significant bit position.
*
* The Andestar v3m architecture has no CLZ instruction (contrary to v3),
* so let's use the software implementation.
*/
int __clzsi2(int x)
{
int r = 0;
if (!x)
return 32;
if (!(x & 0xffff0000u)) {
x <<= 16;
r += 16;
}
if (!(x & 0xff000000u)) {
x <<= 8;
r += 8;
}
if (!(x & 0xf0000000u)) {
x <<= 4;
r += 4;
}
if (!(x & 0xc0000000u)) {
x <<= 2;
r += 2;
}
if (!(x & 0x80000000u)) {
x <<= 1;
r += 1;
}
return r;
}