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This will be used to support ITE IT8380 chip which contains an Andes N801 core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=make BOARD=it8380dev Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce Reviewed-on: https://chromium-review.googlesource.com/175480 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
53 lines
898 B
C
53 lines
898 B
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Set up the N8 core
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*/
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#include "cpu.h"
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void cpu_init(void)
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{
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/* DLM initialization is done in init.S */
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}
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/**
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* Count leading zeros
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*
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* @param x non null integer.
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* @return the number of leading 0-bits in x,
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* starting at the most significant bit position.
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*
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* The Andestar v3m architecture has no CLZ instruction (contrary to v3),
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* so let's use the software implementation.
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*/
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int __clzsi2(int x)
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{
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int r = 0;
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if (!x)
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return 32;
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if (!(x & 0xffff0000u)) {
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x <<= 16;
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r += 16;
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}
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if (!(x & 0xff000000u)) {
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x <<= 8;
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r += 8;
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}
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if (!(x & 0xf0000000u)) {
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x <<= 4;
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r += 4;
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}
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if (!(x & 0xc0000000u)) {
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x <<= 2;
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r += 2;
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}
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if (!(x & 0x80000000u)) {
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x <<= 1;
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r += 1;
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}
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return r;
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}
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