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edbfb3a43b
Add support to enable the architectural D-cache on ARMv7-M CPU supporting it. Update the MPU code in order to be able to declare an 'uncached' RAM region (e.g. to store the DMA buffer). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=with the following CL, on ZerbleBarn, boot and capture a finger image. Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285 Reviewed-on: https://chromium-review.googlesource.com/1032776 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Set up the Cortex-M core
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*/
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#include "common.h"
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#include "cpu.h"
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#include "hooks.h"
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void cpu_init(void)
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{
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/* Catch divide by 0 and unaligned access */
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CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP | CPU_NVIC_CCR_UNALIGN_TRAP;
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/* Enable reporting of memory faults, bus faults and usage faults */
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CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA |
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CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA;
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}
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#ifdef CONFIG_ARMV7M_CACHE
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static void cpu_invalidate_icache(void)
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{
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/*
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* Invalidates the entire instruction cache to the point of
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* unification.
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*/
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CPU_SCB_ICIALLU = 0;
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asm volatile("dsb; isb");
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}
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void cpu_enable_caches(void)
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{
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/* Check whether the I-cache is already enabled */
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if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_ICACHE)) {
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/* Invalidate the I-cache first */
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cpu_invalidate_icache();
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/* Turn on the caching */
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CPU_NVIC_CCR |= CPU_NVIC_CCR_ICACHE;
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asm volatile("dsb; isb");
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}
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/* Check whether the D-cache is already enabled */
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if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_DCACHE)) {
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/* Invalidate the D-cache first */
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cpu_invalidate_dcache();
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/* Turn on the caching */
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CPU_NVIC_CCR |= CPU_NVIC_CCR_DCACHE;
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asm volatile("dsb; isb");
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}
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}
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static void cpu_sysjump_cache(void)
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{
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/*
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* Disable the I-cache and the D-cache
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* The I-cache will be invalidated after the sysjump if needed
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* (e.g after a flash update).
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*/
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cpu_clean_invalidate_dcache();
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CPU_NVIC_CCR &= ~(CPU_NVIC_CCR_ICACHE | CPU_NVIC_CCR_DCACHE);
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asm volatile("dsb; isb");
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}
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DECLARE_HOOK(HOOK_SYSJUMP, cpu_sysjump_cache, HOOK_PRIO_LAST);
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#endif /* CONFIG_ARMV7M_CACHE */
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