Dimitris Papastamos 1d6d47a82a Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75 ...

This patch implements a fast path for this SMC call on affected PEs by
detecting and returning immediately after executing the workaround.

NOTE: The MMU disable/enable workaround now assumes that the MMU was
enabled on entry to EL3.  This is a valid assumption as the code turns
on the MMU after reset and leaves it on until the core powers off.

Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

2018-01-29 09:58:57 +00:00

..

aarch32

ARMv7: division support for missing __aeabi_*divmod

2017-11-08 14:42:07 +01:00

aarch64

Introduce functions to disable the MMU in EL1

2017-10-17 12:02:37 +01:00

compiler-rt

Import ctzdi2.c from LLVM compiler-rt

2017-07-26 09:28:23 +01:00

coreboot

coreboot: Add support for CBMEM console

2018-01-19 15:21:12 -08:00

cpus

Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75

2018-01-29 09:58:57 +00:00

el3_runtime

Enable SVE for Non-secure world

2017-11-30 17:45:09 +00:00

extensions

AMU: Remove unnecessary WARN()

2018-01-15 15:07:06 +00:00

libfdt

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

locks

ARMv7 does not support STL instruction

2017-11-08 13:49:29 +01:00

optee

Add Trusted OS extra image parsing support for ARM standard platforms

2017-08-09 18:06:05 +08:00

pmf

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

psci

Add support for SMCCC_VERSION in PSCI features

2018-01-29 09:58:57 +00:00

semihosting

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

stack_protector

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

stdlib

Use standard UNIX file:line format in assert

2017-07-19 05:57:40 +01:00

utils

Add mem_region utility functions

2017-09-25 13:32:20 +01:00

xlat_tables

Merge pull request #1145 from etienne-lms/rfc-armv7-2

2017-11-23 23:41:24 +00:00

xlat_tables_v2

xlat v2: Correctly unmap regions on map error

2018-01-10 15:39:37 +00:00