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https://github.com/Telecominfraproject/OpenCellular.git
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6473343075
On panic, reboot properly the CPU rather than just jumping to the reset vector as that might lead to some incorrect initializations. Properly plug the div by 0 to the panic handling. Add a small trace if the debug output is activated. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:29840 TEST=add adhoc code triggering a data abort and see the firmware printing a trace, then rebooting immediatly in a working state. Change-Id: I1d5a98d9113c8ae08e05588a40f941d1ed22cebe Reviewed-on: https://chromium-review.googlesource.com/206268 Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
144 lines
2.6 KiB
C
144 lines
2.6 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* tiny substitute of the runtime layer */
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#include "common.h"
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#include "cpu.h"
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#include "debug.h"
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#include "master_slave.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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volatile uint32_t last_event;
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static uint32_t last_deadline;
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static uint8_t need_wfi;
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timestamp_t get_time(void)
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{
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timestamp_t t;
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uint32_t hi, lo;
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do {
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hi = STM32_TIM_CNT(3);
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lo = STM32_TIM_CNT(2);
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} while (hi != STM32_TIM_CNT(3));
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t.le.lo = (hi << 16) | lo;
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t.le.hi = 0;
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return t;
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}
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void udelay(unsigned us)
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{
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unsigned t0 = get_time().le.lo;
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while ((get_time().le.lo - t0) < us)
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;
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}
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void task_enable_irq(int irq)
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{
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CPU_NVIC_EN(0) = 1 << irq;
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}
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void task_disable_irq(int irq)
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{
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CPU_NVIC_DIS(0) = 1 << irq;
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}
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void task_clear_pending_irq(int irq)
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{
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CPU_NVIC_UNPEND(0) = 1 << irq;
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}
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uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
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{
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last_event = event;
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return 0;
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}
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void tim2_interrupt(void)
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{
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if (STM32_TIM_CNT(3) == last_deadline >> 16) {
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STM32_TIM_DIER(2) = 0;
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task_clear_pending_irq(STM32_IRQ_TIM2);
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last_event = 1 << 29 /* task event wake */;
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need_wfi = 0;
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} else {
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need_wfi = 1;
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}
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}
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DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1);
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void __hw_clock_event_set(uint32_t deadline)
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{
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last_deadline = deadline;
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STM32_TIM_CCR1(2) = deadline & 0xffff;
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STM32_TIM_SR(2) = ~2;
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STM32_TIM_DIER(2) |= 2;
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}
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uint32_t task_wait_event(int timeout_us)
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{
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uint32_t evt;
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/* the event already happened */
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if (last_event || !timeout_us) {
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evt = last_event;
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last_event = 0;
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return evt;
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}
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/* set timeout on timer */
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if (timeout_us > 0)
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__hw_clock_event_set(get_time().le.lo + timeout_us);
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do {
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/* sleep until next interrupt */
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asm volatile("wfi");
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} while (need_wfi);
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STM32_TIM_DIER(2) = 0; /* disable match interrupt */
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evt = last_event;
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last_event = 0;
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return evt;
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}
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void system_reboot(void)
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{
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if (master_slave_is_master()) {
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/* Ask the slave to reboot as well */
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STM32_GPIO_BSRR(GPIO_A) = 1 << (6 + 16);
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udelay(10 * MSEC); /* The slave reboots in 5 ms */
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}
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/* Ask the watchdog to trigger a hard reboot */
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STM32_IWDG_KR = 0x5555;
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STM32_IWDG_RLR = 0x1;
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STM32_IWDG_KR = 0xcccc;
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/* wait for the watchdog */
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while (1)
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;
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}
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/* Unhandled exception panic */
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void exception_panic(void)
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{
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debug_printf("PANIC\n");
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system_reboot();
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}
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/* --- stubs --- */
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void __hw_timer_enable_clock(int n, int enable)
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{ /* Done in hardware init */ }
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void usleep(unsigned us)
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{ /* Used only as a workaround */ }
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