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9c24fac505
Since the interrupts of MIWU group E/F/G/H of table 0 are the same (interrupt 11), we need to handle LPCs' and GPIOs' events at the same ISR. But we also found there is a leak that ec has the chance to skip the other events which don't belong to GPIOs unexpectedly. (For example, LRESET and eSPI Reset) This CL fixed this issue by only clearing pending bits belong to GPIOs in their ISRs. BRANCH=none BUG=b:35648154 TEST=passed warm-reset testing on pyro over 12 hours. Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/449472 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>