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3405c79584
This change is a safegaurd to ensure that TPM register data is always placed in the correct location in the HW read I2CS fifo. It is only checked for 1 or 4 byte regsiter reads. Because of the way in which a TPM command is sent and the response is read, there are multiple reads of the STS register prior to reading the TPM fifo register. Therefore ensuring the fifo has zero depth when 1 or 4 byte regsiter reads, improves the robustness of the design. Added a counter to track the number of times the fifo is adjusted and a new console command 'i2cs disp|rst' to display the count and reset it to 0 if desired. Removed section in code for TPM fifo register reads intended to handle the case where there was a mismatch between how many bytes were copied into the fifo and the number read by the host. Since the burstcount field in the status register always contains a valid amount of data that can be read by the host, there should not be cases where the host reads less data than was copied from the TPM fifo register. In the unexpected cases where the host may not drain all of the I2CS read fifo data during a TPM register read, the I2CS fifo depth will be corrected the next time that it reads either the access or STS register which happens prior to the start of any TPM transaction. BRANCH=none BUG=chrome-os-partner:57338,chrome-os-partner:59191 TEST=manual Booted Reef and verfied that TPM functionality is working. Change-Id: I065a55e64bbcc0cb3357a2bd83447a05400b8899 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382689 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CHIP_G_I2CS_H
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#define __CHIP_G_I2CS_H
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#include <stddef.h>
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/*
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* Write complete interrupt callback function prototype. This function expects
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* two parameters: the address of the buffer containing received data and
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* number of bytes in the buffer.
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*/
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typedef void (*wr_complete_handler_f)(void *i2cs_data, size_t i2cs_data_size);
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/* Register the write complete interrupt handler. */
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int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler);
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/*
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* Post a byte for the master to read. Blend the byte into the appropriate
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* 4byte register of the master read register file.
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*/
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void i2cs_post_read_data(uint8_t byte_to_read);
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/*
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* Configure the pinmux registers required to connect the I2CS interface. This
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* function is board specific and so it exists in the associated board.c file.
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*/
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void i2cs_set_pinmux(void);
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/*
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* Ensure no bytes are currently buffered in the I2CS READ fifo. This
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* value is calculated by finding the difference between read pointer that's
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* used by FW to add bytes to the HW fifo and the current value of the
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* I2CS_READ_PTR register.
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*
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* @returns: the number of bytes buffered when the function is called
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*/
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size_t i2cs_zero_read_fifo_buffer_depth(void);
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/*
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* Write buffer of data into the I2CS HW read fifo. The function will operate a
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* byte at a time until the fifo write pointer is word aligned. Then it will
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* consume all remaining words of input data. There is another stage to handle
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* any excess bytes. The efficiency benefits relative the byte at a time
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* function diminish as the buffer size gets smaller and therefore not intended
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* to be used for <= 4 byte buffers.
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*/
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void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len);
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#endif /* ! __CHIP_G_I2CS_H */
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