Patrick Georgi 5c406459e8 Enable MULTIPLE_CBFS_INSTANCES on x86, too ...

It works there, we want it, disable that restriction.

Change-Id: Idc023775f0750c980c989bff10486550e4ad1374
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/12094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

2015-10-20 16:39:00 +02:00

..

acpi

acpi/sata: add generic sata ssdt port generator

2015-06-07 01:24:47 +02:00

arch

armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write

2015-10-17 18:10:29 +00:00

commonlib

vboot: prepare for x86 verstage

2015-10-11 23:57:29 +00:00

console

x86: add standalone verstage support

2015-10-14 17:07:52 +00:00

cpu

cpu/amd/model_10xxx: Install AMD-provided microcode files in CBFS

2015-10-16 02:41:37 +00:00

device

x86: add standalone verstage support

2015-10-14 17:07:52 +00:00

drivers

cpu/mtrr.h: Fix macro names for MTRR registers

2015-10-15 03:52:49 +00:00

ec

ec/google: Move label to BOL to satisfy lint-tests

2015-10-15 07:36:26 +00:00

include

cpu/mtrr.h: Fix macro names for MTRR registers

2015-10-15 03:52:49 +00:00

lib

Revert "coreboot_table: don't add CMOS checksum twice."

2015-10-20 16:35:12 +02:00

mainboard

kontron/ktqm77: Tag all four USB3 ports switchable and SS capable

2015-10-17 06:28:30 +00:00

northbridge

cpu/mtrr.h: Fix macro names for MTRR registers

2015-10-15 03:52:49 +00:00

soc

soc/intel/broadwell: fix USBDEBUG copy-pasta

2015-10-15 17:48:17 +00:00

southbridge

intel/southbridge/bd82x6x: Add option to set SPI VSCC registers

2015-10-16 22:47:22 +00:00

superio

superio/smsc: Add support for SMSC DME1737

2015-07-13 17:11:00 +02:00

vendorcode

vendorcode/google: Deal with MULTIPLE_CBFS_INSTANCES

2015-10-19 21:09:30 +02:00

Kconfig

Enable MULTIPLE_CBFS_INSTANCES on x86, too

2015-10-20 16:39:00 +02:00