Andrey Petrov a6dd535354 drivers/intel/fsp2_0: Add boot mode constants ...

This adds boot mode constants. They match EDK2 found in PiBootMode.h
constants but are part of FSP2.0 spec.

Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

2016-04-08 00:33:55 +02:00

..

acpi

acpi/: add missing license header

2016-01-14 22:52:11 +01:00

arch

arch/power8: Position bootblock start at reset vector

2016-04-04 20:45:19 +02:00

commonlib

arch/x86: introduce postcar stage/phase

2016-03-23 14:24:30 +01:00

console

arch/x86: introduce postcar stage/phase

2016-03-23 14:24:30 +01:00

cpu

src/: Fix lint style-labels warnings

2016-03-31 23:05:32 +02:00

device

device: Add i2c read/write register field API

2016-03-21 23:10:55 +01:00

drivers

drivers/intel/fsp2_0: Add boot mode constants

2016-04-08 00:33:55 +02:00

ec

Hide EC_GOOGLE_CHROMEEC_SPI_BUS.

2016-03-05 00:57:22 +01:00

include

edid: Make framebuffer row alignment configurable

2016-04-07 20:46:38 +02:00

lib

edid: Make framebuffer row alignment configurable

2016-04-07 20:46:38 +02:00

mainboard

mainboard/intel/apollolake_rvp: Include FADT tables

2016-04-07 22:46:28 +02:00

northbridge

nb/intel/sandybridge/raminit: die in toplevel function

2016-04-05 22:54:30 +02:00

soc

rockchip: refactor to sharing code among similar SOCs

2016-04-07 21:49:20 +02:00

southbridge

sb/amd/sb700: Enable reset on sync flood

2016-04-07 18:56:33 +02:00

superio

superio/nuvoton: Use official spelling of Nuvoton in CHIP_NAME

2016-04-02 04:10:07 +02:00

vendorcode

chromeos: Fix adding a bmpblk to GBB

2016-04-05 13:37:11 +02:00

Kconfig

Kconfig: remove COMPRESS_PRERAM_STAGES option from x86

2016-03-11 16:52:38 +01:00