Brenton Dong c9b398191e soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init ...

FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram.  Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-12-21 00:11:24 +01:00

..

arm

buildsystem: Drop explicit (k)config.h includes

2016-12-08 19:46:53 +01:00

arm64

buildsystem: Drop explicit (k)config.h includes

2016-12-08 19:46:53 +01:00

mips

build system: remove CBFSTOOL_PRE1_OPTS

2016-05-03 11:40:49 +02:00

power8

region: Add writeat and eraseat support

2016-06-24 20:48:12 +02:00

riscv

riscv: enable counters via m[us]counteren

2016-12-20 00:10:33 +01:00

x86

soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init

2016-12-21 00:11:24 +01:00