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The timer clock nominally requires no firmware settings. It is tuned in manufacturing to be centered around 24MHz. However, it will potentially migrate away from 24MHz based upon variations in temperature and voltage. The variation is approximately 0.1-0.5MHz, based upon functional simulations, and backed up with observations in the lab. This CL enables a hardware feature to dynamically tune the timer clock if the device has an active USB port, by monitoring the SOF (start of frame) USB packets that are sent by the USB host every milllsecond with 500ppm accuracy. BUG=chrome-os-partner:50800 BRANCH=none TEST=make buildall; run on Cr50 hardware Verified that deep sleep, USB suspend/resume, etc continue to work with this enabled. Not too surprising, since I've never encountered a problem without it. In addition, I monitored XO_CLK_TIMER_CURRENT to see that the timer adjustments are being made while connecting and disconnecting from USB, entering andleaving sleep and deep sleep, etc. They are. Change-Id: I328b6416bc40ef8718815c5e09cf91ec1c6646f0 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342145 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
13 lines
335 B
C
13 lines
335 B
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_INIT_CHIP_H
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#define __CROS_EC_INIT_CHIP_H
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void init_jittery_clock(int highsec);
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void init_sof_clock(void);
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#endif /* __CROS_EC_INIT_CHIP_H */
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