Isla Mitchell abbffe98ed Add support for Cortex-Ares and Cortex-A76 CPUs ...

Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU).  The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are simple.

Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

2018-06-08 11:46:31 +01:00

..

bl1

Fix MISRA rule 8.4 Part 1

2018-02-28 17:19:55 +00:00

bl2

Fix MISRA rule 8.5 in common code

2018-04-13 14:01:56 +01:00

bl2u

Fix MISRA rule 8.4 in common code

2018-02-28 17:18:46 +00:00

bl31

RAS: Allow individual interrupt registration

2018-05-04 08:33:17 +01:00

bl32

Introduce the new BL handover interface

2018-02-26 16:31:10 +00:00

common

Merge pull request #1386 from soby-mathew/sm/dyn_bl31

2018-05-23 12:45:13 +01:00

drivers

Ensure read and write of flags are 32 bit

2018-05-17 16:42:41 +01:00

lib

Add support for Cortex-Ares and Cortex-A76 CPUs

2018-06-08 11:46:31 +01:00

plat

ARM platforms: Move BL31 below BL2 to enable BL2 overlay

2018-06-07 12:26:19 +01:00

services

Merge pull request #1392 from dp-arm/dp/cve_2018_3639

2018-05-29 09:28:05 +01:00

tools_share

Dynamic cfg: Enable support on CoT for other configs

2018-05-18 12:26:38 +01:00