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This adds SPI transaction support, and a debug command to read a few values from the SPI EEPROM. Note that the SPI controller is normally *disabled* with all its I/Os high-Z, so this will not interfere with main processor or Servo on the SPI bus. The bus is only enabled during the SPIROM command itself. BUG=chrome-os-partner:7844 TEST=manual 1) Reboot system 2) on EC console, 'spirom'. Should print Man/Dev ID : 0xef 0x16 JEDEC ID : 0xef 0x40 0x17 Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32 Status reg 1: 0x00 Status reg 2: 0x00 Note that unique ID is, well, unique, so it won't match my value. But it should still be something not all 0xff's. 3) Power on the system. x86 should still boot normally, indicating that the EC isn't interfering with the SPI bus. Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8
23 lines
812 B
C
23 lines
812 B
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* SPI interface for Chrome EC */
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#ifndef __CROS_EC_SPI_H
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#define __CROS_EC_SPI_H
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/* Enable / disable the SPI port. When the port is disabled, all its I/O lines
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* are high-Z so the EC won't interfere with other devices on the SPI bus. */
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int spi_enable(int enable);
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/* Issue a SPI transaction. Assumes SPI port has already been enabled.
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* Transmits <txlen> bytes from <txdata>, throwing away the corresponding
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* received data, then transmits <rxlen> dummy bytes, saving the received data
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* in <rxdata>. */
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int spi_transaction(const uint8_t *txdata, int txlen,
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uint8_t *rxdata, int rxlen);
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#endif /* __CROS_EC_SPI_H */
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