Lijian Zhao ae565463b6 soc/intel/cannonlake: Add all the SOC level DSDT tables ...

Add all the SOC level DSDT tables, reference from skylake/kabylake. 

Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2017-10-05 21:16:46 +00:00

..

acpi

src/acpi: Add guards on all header files

2017-08-01 23:04:27 +00:00

arch

arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers

2017-09-27 16:41:03 +00:00

commonlib

commonlib: Consistently spell *romstage* without space

2017-09-27 22:20:25 +00:00

console

console: Ignore loglevel in nvram until ramstage

2017-09-25 13:35:29 +00:00

cpu

AGESA vendorcode: Add ENABLE_MRC_CACHE option

2017-10-05 13:23:27 +00:00

device

device/dram/ddr2.c: fix a hidden syntax error introduced earlier

2017-09-26 15:53:55 +00:00

drivers

chromeec: Remove checks for EC in RO

2017-10-04 20:55:12 +00:00

ec

chromeec: Remove checks for EC in RO

2017-10-04 20:55:12 +00:00

include

cpu/amd/amdfam15: Add misc. SMM definitions

2017-09-27 15:57:16 +00:00

lib

Kconfig: Move libhwbase related options into lib/Kconfig

2017-09-28 11:47:07 +00:00

mainboard

src/mainboard/Kconfig: Add support for 10240 KiB ROM chips

2017-10-05 17:53:16 +00:00

northbridge

nb/intel/gm45: Remove UMA alignment optimization

2017-10-03 19:48:01 +00:00

soc

soc/intel/cannonlake: Add all the SOC level DSDT tables

2017-10-05 21:16:46 +00:00

southbridge

smbus: Fix a typo ("Set the device I'm talking too")

2017-09-27 16:38:18 +00:00

superio

winbond/w83627hf: Drop early_init.c

2017-09-21 15:40:49 +00:00

vboot

chromeec: Remove checks for EC in RO

2017-10-04 20:55:12 +00:00

vendorcode

vendor/intel/skykabylake: Update FSP header files to version 2.7.2

2017-10-05 17:45:46 +00:00

Kconfig

Kconfig: Move libhwbase related options into lib/Kconfig

2017-09-28 11:47:07 +00:00