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f23f45e74e
The ARMv7-M ISA defines standard (and optional) mechanism to manage the CPU caches through the SCB (System Control Block) registers. So far, only the Cortex-M7 core implements such as a mechanism (e.g. the Cortex-M4 with caches we have are using a proprietary mechanism for the management). Define the functions to use the I-Cache, and enable them on STM32H7 which is our only supported Cortex-M7 core. The D-Cache mechanism is still To Be Done, as it involves a bit more support in the firmware for the DMA memory areas. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR (e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload without crash and with a speed-up. Change-Id: I6af1021d65048b787630387f7d95797db15d069c Reviewed-on: https://chromium-review.googlesource.com/943445 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
57 lines
1.4 KiB
C
57 lines
1.4 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Set up the Cortex-M core
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*/
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#include "common.h"
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#include "cpu.h"
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#include "hooks.h"
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void cpu_init(void)
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{
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/* Catch divide by 0 and unaligned access */
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CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP | CPU_NVIC_CCR_UNALIGN_TRAP;
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/* Enable reporting of memory faults, bus faults and usage faults */
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CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA |
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CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA;
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}
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#ifdef CONFIG_ARMV7M_CACHE
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static void cpu_invalidate_icache(void)
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{
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/*
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* Invalidates the entire instruction cache to the point of
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* unification.
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*/
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CPU_SCB_ICIALLU = 0;
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asm volatile("dsb; isb");
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}
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void cpu_enable_icache(void)
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{
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/* Check whether the I-cache is already enabled */
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if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_ICACHE)) {
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/* Invalidate the I-cache first */
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cpu_invalidate_icache();
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/* Turn on the caching */
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CPU_NVIC_CCR |= CPU_NVIC_CCR_ICACHE;
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asm volatile("dsb; isb");
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}
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}
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static void cpu_sysjump_cache(void)
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{
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/*
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* Disable the I-cache
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* so we will invalidate it after the sysjump if needed
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* (e.g after a flash update).
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*/
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CPU_NVIC_CCR &= ~CPU_NVIC_CCR_ICACHE;
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asm volatile("dsb; isb");
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}
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DECLARE_HOOK(HOOK_SYSJUMP, cpu_sysjump_cache, HOOK_PRIO_LAST);
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#endif /* CONFIG_ARMV7M_CACHE */
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