Soby Mathew b1a9631d81 Optimize barrier usage during Cortex-A57 power down ...

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d

2014-10-29 17:38:56 +00:00

..

aarch64

Add support for level specific cache maintenance operations

2014-10-29 17:38:56 +00:00

cpus

Optimize barrier usage during Cortex-A57 power down

2014-10-29 17:38:56 +00:00

locks

Remove calling CPU mpidr from bakery lock API

2014-06-23 23:16:39 +01:00

semihosting

Remove extern keyword from function declarations

2014-05-23 12:15:54 +01:00

stdlib

Rationalize console log output

2014-08-12 16:51:18 +01:00