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https://github.com/Telecominfraproject/OpenCellular.git
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5fd3341077
Allow flashing the RW firmware by sending Vendor-Defined Messages over the USB-PD link. This is not the secure update whose design is still under discussion, it's a simple update with integrity check. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28330 TEST=using the following CLs, ./util/flash_pd.py ./build/zinger/ec.RW.flat and see Zinger booting on RW, repeat the operations with different builds of the RW firmware. Change-Id: Icd90eb92f7321ccd66341a50b9dabd73c59c68c1 Reviewed-on: https://chromium-review.googlesource.com/197948 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
111 lines
2.1 KiB
C
111 lines
2.1 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* tiny substitute of the runtime layer */
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#include "common.h"
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#include "cpu.h"
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#include "debug.h"
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#include "irq_handler.h"
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#include "registers.h"
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#include "timer.h"
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#include "util.h"
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volatile uint32_t last_event;
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timestamp_t get_time(void)
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{
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timestamp_t t;
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t.le.lo = STM32_TIM32_CNT(2);
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t.le.hi = 0;
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return t;
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}
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void udelay(unsigned us)
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{
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unsigned t0 = STM32_TIM32_CNT(2);
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while ((STM32_TIM32_CNT(2) - t0) < us)
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;
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}
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void task_enable_irq(int irq)
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{
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CPU_NVIC_EN(0) = 1 << irq;
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}
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void task_disable_irq(int irq)
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{
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CPU_NVIC_DIS(0) = 1 << irq;
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}
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void task_clear_pending_irq(int irq)
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{
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CPU_NVIC_UNPEND(0) = 1 << irq;
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}
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uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
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{
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last_event = event;
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return 0;
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}
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void IRQ_HANDLER(STM32_IRQ_TIM2)(void)
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{
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STM32_TIM_DIER(2) = 0; /* disable match interrupt */
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task_clear_pending_irq(STM32_IRQ_TIM2);
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last_event = 1 << 29 /* task event wake */;
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}
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uint32_t task_wait_event(int timeout_us)
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{
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uint32_t evt;
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asm volatile("cpsid i");
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/* the event already happened */
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if (last_event || !timeout_us) {
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evt = last_event;
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last_event = 0;
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asm volatile("cpsie i ; isb");
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return evt;
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}
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/* set timeout on timer */
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if (timeout_us > 0) {
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STM32_TIM32_CCR1(2) = STM32_TIM32_CNT(2) + timeout_us;
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STM32_TIM_SR(2) = 0; /* clear match flag */
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STM32_TIM_DIER(2) = 2; /* match interrupt */
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}
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/* sleep until next interrupt */
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asm volatile("wfi");
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STM32_TIM_DIER(2) = 0; /* disable match interrupt */
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evt = last_event;
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last_event = 0;
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asm volatile("cpsie i ; isb");
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return evt;
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}
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void cpu_reset(void)
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{
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/* Disable interrupts */
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asm volatile("cpsid i");
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/* reboot the CPU */
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CPU_NVIC_APINT = 0x05fa0004;
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/* Spin and wait for reboot; should never return */
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while (1)
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;
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}
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/* --- stubs --- */
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void __hw_timer_enable_clock(int n, int enable)
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{ /* Done in hardware init */ }
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void usleep(unsigned us)
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{ /* Used only as a workaround */ }
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